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4 | 4 | */
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5 | 5 |
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6 | 6 | #include <linux/clk.h>
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| 7 | +#include <linux/dma-mapping.h> |
| 8 | +#include <linux/mailbox_controller.h> |
7 | 9 | #include <linux/pm_runtime.h>
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8 | 10 | #include <linux/soc/mediatek/mtk-cmdq.h>
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9 | 11 | #include <linux/soc/mediatek/mtk-mmsys.h>
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@@ -222,9 +224,11 @@ struct mtk_ddp_comp *mtk_drm_ddp_comp_for_plane(struct drm_crtc *crtc,
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222 | 224 | }
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223 | 225 |
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224 | 226 | #if IS_REACHABLE(CONFIG_MTK_CMDQ)
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225 |
| -static void ddp_cmdq_cb(struct cmdq_cb_data data) |
| 227 | +static void ddp_cmdq_cb(struct mbox_client *cl, void *mssg) |
226 | 228 | {
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227 |
| - cmdq_pkt_destroy(data.data); |
| 229 | + struct cmdq_cb_data *data = mssg; |
| 230 | + |
| 231 | + cmdq_pkt_destroy(data->pkt); |
228 | 232 | }
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229 | 233 | #endif
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230 | 234 |
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@@ -475,7 +479,12 @@ static void mtk_drm_crtc_update_config(struct mtk_drm_crtc *mtk_crtc,
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475 | 479 | cmdq_pkt_wfe(cmdq_handle, mtk_crtc->cmdq_event, false);
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476 | 480 | mtk_crtc_ddp_config(crtc, cmdq_handle);
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477 | 481 | cmdq_pkt_finalize(cmdq_handle);
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478 |
| - cmdq_pkt_flush_async(cmdq_handle, ddp_cmdq_cb, cmdq_handle); |
| 482 | + dma_sync_single_for_device(mtk_crtc->cmdq_client->chan->mbox->dev, |
| 483 | + cmdq_handle->pa_base, |
| 484 | + cmdq_handle->cmd_buf_size, |
| 485 | + DMA_TO_DEVICE); |
| 486 | + mbox_send_message(mtk_crtc->cmdq_client->chan, cmdq_handle); |
| 487 | + mbox_client_txdone(mtk_crtc->cmdq_client->chan, 0); |
479 | 488 | }
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480 | 489 | #endif
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481 | 490 | mtk_crtc->config_updating = false;
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@@ -842,6 +851,7 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
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842 | 851 | }
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843 | 852 |
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844 | 853 | if (mtk_crtc->cmdq_client) {
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| 854 | + mtk_crtc->cmdq_client->client.rx_callback = ddp_cmdq_cb; |
845 | 855 | ret = of_property_read_u32_index(priv->mutex_node,
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846 | 856 | "mediatek,gce-events",
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847 | 857 | drm_crtc_index(&mtk_crtc->base),
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