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Merge tag 'mvebu-dt64-5.15-1' of git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu into arm/dt
mvebu dt64 for 5.15 (part 1) - DTS updates for Marvell Armada CN913x platforms + Add support for Armada CN913x Development Board topology "B" + Add support for Armada CN913x Reference Design boards (CRB) + Fixes the NAND partitioning scheme in DTS eliminating gap between consecutive partitions + Fix 10Gb ports PHY mode names - Extend PCIe MEM space on Armada 37xx: useful for some combination of PCIe cards where the initial 16MB was not enough * tag 'mvebu-dt64-5.15-1' of git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu: arm64: dts: marvell: armada-37xx: Extend PCIe MEM space arch/arm64: dts: change 10gbase-kr to 10gbase-r in Armada arm64: dts: add support for Marvell cn9130-crb platform dts: marvell: Enable 10G interfaces on 9130-DB and 9131-DB boards arm64: dts: cn913x: add device trees for topology B boards Link: https://lore.kernel.org/r/878s10ypxe.fsf@BL-laptop Signed-off-by: Arnd Bergmann <[email protected]>
2 parents 911f0fa + 514ef1e commit c4d3928

17 files changed

+1267
-805
lines changed

‎arch/arm64/boot/dts/marvell/Makefile

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@@ -16,5 +16,10 @@ dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-mcbin-singleshot.dtb
1616
dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-puzzle-m801.dtb
1717
dtb-$(CONFIG_ARCH_MVEBU) += armada-8080-db.dtb
1818
dtb-$(CONFIG_ARCH_MVEBU) += cn9130-db.dtb
19+
dtb-$(CONFIG_ARCH_MVEBU) += cn9130-db-B.dtb
1920
dtb-$(CONFIG_ARCH_MVEBU) += cn9131-db.dtb
21+
dtb-$(CONFIG_ARCH_MVEBU) += cn9131-db-B.dtb
2022
dtb-$(CONFIG_ARCH_MVEBU) += cn9132-db.dtb
23+
dtb-$(CONFIG_ARCH_MVEBU) += cn9132-db-B.dtb
24+
dtb-$(CONFIG_ARCH_MVEBU) += cn9130-crb-A.dtb
25+
dtb-$(CONFIG_ARCH_MVEBU) += cn9130-crb-B.dtb

‎arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts

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@@ -132,6 +132,23 @@
132132
pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>;
133133
status = "okay";
134134
reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>;
135+
/*
136+
* U-Boot port for Turris Mox has a bug which always expects that "ranges" DT property
137+
* contains exactly 2 ranges with 3 (child) address cells, 2 (parent) address cells and
138+
* 2 size cells and also expects that the second range starts at 16 MB offset. If these
139+
* conditions are not met then U-Boot crashes during loading kernel DTB file. PCIe address
140+
* space is 128 MB long, so the best split between MEM and IO is to use fixed 16 MB window
141+
* for IO and the rest 112 MB (64+32+16) for MEM, despite that maximal IO size is just 64 kB.
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* This bug is not present in U-Boot ports for other Armada 3700 devices and is fixed in
143+
* U-Boot version 2021.07. See relevant U-Boot commits (the last one contains fix):
144+
* https://source.denx.de/u-boot/u-boot/-/commit/cb2ddb291ee6fcbddd6d8f4ff49089dfe580f5d7
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* https://source.denx.de/u-boot/u-boot/-/commit/c64ac3b3185aeb3846297ad7391fc6df8ecd73bf
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* https://source.denx.de/u-boot/u-boot/-/commit/4a82fca8e330157081fc132a591ebd99ba02ee33
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*/
148+
#address-cells = <3>;
149+
#size-cells = <2>;
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ranges = <0x81000000 0 0xe8000000 0 0xe8000000 0 0x01000000 /* Port 0 IO */
151+
0x82000000 0 0xe9000000 0 0xe9000000 0 0x07000000>; /* Port 0 MEM */
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136153
/* enabled by U-Boot if PCIe module is present */
137154
status = "disabled";

‎arch/arm64/boot/dts/marvell/armada-37xx.dtsi

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Original file line numberDiff line numberDiff line change
@@ -489,8 +489,15 @@
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#interrupt-cells = <1>;
490490
msi-parent = <&pcie0>;
491491
msi-controller;
492-
ranges = <0x82000000 0 0xe8000000 0 0xe8000000 0 0x1000000 /* Port 0 MEM */
493-
0x81000000 0 0xe9000000 0 0xe9000000 0 0x10000>; /* Port 0 IO*/
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/*
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* The 128 MiB address range [0xe8000000-0xf0000000] is
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* dedicated for PCIe and can be assigned to 8 windows
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* with size a power of two. Use one 64 KiB window for
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* IO at the end and the remaining seven windows
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* (totaling 127 MiB) for MEM.
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*/
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ranges = <0x82000000 0 0xe8000000 0 0xe8000000 0 0x07f00000 /* Port 0 MEM */
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0x81000000 0 0xefff0000 0 0xefff0000 0 0x00010000>; /* Port 0 IO */
494501
interrupt-map-mask = <0 0 0 7>;
495502
interrupt-map = <0 0 0 1 &pcie_intc 0>,
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<0 0 0 2 &pcie_intc 1>,

‎arch/arm64/boot/dts/marvell/armada-7040-db.dts

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@@ -282,7 +282,7 @@
282282
&cp0_eth0 {
283283
status = "okay";
284284
/* Network PHY */
285-
phy-mode = "10gbase-kr";
285+
phy-mode = "10gbase-r";
286286
/* Generic PHY, providing serdes lanes */
287287
phys = <&cp0_comphy2 0>;
288288

‎arch/arm64/boot/dts/marvell/armada-8040-db.dts

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@@ -195,7 +195,7 @@
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196196
&cp0_eth0 {
197197
status = "okay";
198-
phy-mode = "10gbase-kr";
198+
phy-mode = "10gbase-r";
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200200
fixed-link {
201201
speed = <10000>;
@@ -348,7 +348,7 @@
348348

349349
&cp1_eth0 {
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status = "okay";
351-
phy-mode = "10gbase-kr";
351+
phy-mode = "10gbase-r";
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fixed-link {
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speed = <10000>;

‎arch/arm64/boot/dts/marvell/cn9130-crb-A.dts

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@@ -0,0 +1,38 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2020 Marvell International Ltd.
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*/
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6+
#include "cn9130-crb.dtsi"
7+
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/ {
9+
model = "Marvell Armada CN9130-CRB-A";
10+
};
11+
12+
&cp0_pcie0 {
13+
status = "okay";
14+
num-lanes = <4>;
15+
num-viewport = <8>;
16+
/* Generic PHY, providing serdes lanes */
17+
phys = <&cp0_comphy0 0
18+
&cp0_comphy1 0
19+
&cp0_comphy2 0
20+
&cp0_comphy3 0>;
21+
iommu-map =
22+
<0x0 &smmu 0x480 0x20>,
23+
<0x100 &smmu 0x4a0 0x20>,
24+
<0x200 &smmu 0x4c0 0x20>;
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iommu-map-mask = <0x031f>;
26+
};
27+
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&cp0_usb3_0 {
29+
status = "okay";
30+
usb-phy = <&cp0_usb3_0_phy0>;
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phy-names = "usb";
32+
};
33+
34+
&cp0_usb3_1 {
35+
status = "okay";
36+
usb-phy = <&cp0_usb3_0_phy1>;
37+
phy-names = "usb";
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};

‎arch/arm64/boot/dts/marvell/cn9130-crb-B.dts

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// SPDX-License-Identifier: GPL-2.0+
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/*
3+
* Copyright (C) 2020 Marvell International Ltd.
4+
*/
5+
6+
#include "cn9130-crb.dtsi"
7+
8+
/ {
9+
model = "Marvell Armada CN9130-CRB-B";
10+
};
11+
12+
&cp0_pcie0 {
13+
status = "okay";
14+
num-lanes = <1>;
15+
num-viewport = <8>;
16+
/* Generic PHY, providing serdes lanes */
17+
phys = <&cp0_comphy0 0>;
18+
iommu-map =
19+
<0x0 &smmu 0x480 0x20>,
20+
<0x100 &smmu 0x4a0 0x20>,
21+
<0x200 &smmu 0x4c0 0x20>;
22+
iommu-map-mask = <0x031f>;
23+
};
24+
25+
&cp0_sata0 {
26+
status = "okay";
27+
sata-port@0 {
28+
status = "okay";
29+
/* Generic PHY, providing serdes lanes */
30+
phys = <&cp0_comphy2 0>;
31+
};
32+
};
33+
34+
&cp0_usb3_0 {
35+
status = "okay";
36+
usb-phy = <&cp0_usb3_0_phy0>;
37+
phy-names = "usb";
38+
phys = <&cp0_comphy1 0>;
39+
};
40+
41+
&cp0_usb3_1 {
42+
status = "okay";
43+
usb-phy = <&cp0_usb3_0_phy1>;
44+
phy-names = "usb";
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phys = <&cp0_comphy3 1>;
46+
};

‎arch/arm64/boot/dts/marvell/cn9130-crb.dtsi

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@@ -0,0 +1,222 @@
1+
// SPDX-License-Identifier: GPL-2.0+
2+
/*
3+
* Copyright (C) 2020 Marvell International Ltd.
4+
*/
5+
6+
#include "cn9130.dtsi" /* include SoC device tree */
7+
8+
#include <dt-bindings/gpio/gpio.h>
9+
10+
/ {
11+
chosen {
12+
stdout-path = "serial0:115200n8";
13+
};
14+
15+
aliases {
16+
i2c0 = &cp0_i2c0;
17+
ethernet0 = &cp0_eth0;
18+
ethernet1 = &cp0_eth1;
19+
ethernet2 = &cp0_eth2;
20+
};
21+
22+
memory@00000000 {
23+
device_type = "memory";
24+
reg = <0x0 0x0 0x0 0x80000000>;
25+
};
26+
27+
ap0_reg_mmc_vccq: ap0_mmc_vccq@0 {
28+
compatible = "regulator-gpio";
29+
regulator-name = "ap0_mmc_vccq";
30+
regulator-min-microvolt = <1800000>;
31+
regulator-max-microvolt = <3300000>;
32+
gpios = <&expander0 5 GPIO_ACTIVE_HIGH>;
33+
states = <1800000 0x1
34+
3300000 0x0>;
35+
};
36+
37+
cp0_reg_usb3_vbus1: cp0_usb3_vbus@1 {
38+
compatible = "regulator-fixed";
39+
regulator-name = "cp0-xhci1-vbus";
40+
regulator-min-microvolt = <5000000>;
41+
regulator-max-microvolt = <5000000>;
42+
enable-active-high;
43+
gpio = <&expander0 8 GPIO_ACTIVE_HIGH>;
44+
};
45+
46+
cp0_usb3_0_phy0: cp0_usb3_phy0 {
47+
compatible = "usb-nop-xceiv";
48+
};
49+
50+
cp0_usb3_0_phy1: cp0_usb3_phy1 {
51+
compatible = "usb-nop-xceiv";
52+
vcc-supply = <&cp0_reg_usb3_vbus1>;
53+
};
54+
55+
cp0_reg_sd_vccq: cp0_sd_vccq@0 {
56+
compatible = "regulator-gpio";
57+
regulator-name = "cp0_sd_vccq";
58+
regulator-min-microvolt = <1800000>;
59+
regulator-max-microvolt = <3300000>;
60+
gpios = <&cp0_gpio2 18 GPIO_ACTIVE_HIGH>;
61+
states = <1800000 0x1
62+
3300000 0x0>;
63+
};
64+
65+
cp0_reg_sd_vcc: cp0_sd_vcc@0 {
66+
compatible = "regulator-fixed";
67+
regulator-name = "cp0_sd_vcc";
68+
regulator-min-microvolt = <3300000>;
69+
regulator-max-microvolt = <3300000>;
70+
gpio = <&cp0_gpio2 19 GPIO_ACTIVE_HIGH>;
71+
enable-active-high;
72+
regulator-always-on;
73+
};
74+
};
75+
76+
&uart0 {
77+
status = "okay";
78+
};
79+
80+
/* on-board eMMC U6 */
81+
&ap_sdhci0 {
82+
pinctrl-names = "default";
83+
bus-width = <8>;
84+
status = "okay";
85+
mmc-ddr-1_8v;
86+
vqmmc-supply = <&ap0_reg_mmc_vccq>;
87+
};
88+
89+
&cp0_syscon0 {
90+
cp0_pinctrl: pinctrl {
91+
compatible = "marvell,cp115-standalone-pinctrl";
92+
93+
cp0_i2c0_pins: cp0-i2c-pins-0 {
94+
marvell,pins = "mpp37", "mpp38";
95+
marvell,function = "i2c0";
96+
};
97+
cp0_i2c1_pins: cp0-i2c-pins-1 {
98+
marvell,pins = "mpp35", "mpp36";
99+
marvell,function = "i2c1";
100+
};
101+
cp0_sdhci_cd_pins_crb: cp0-sdhci-cd-pins-crb {
102+
marvell,pins = "mpp55";
103+
marvell,function = "gpio";
104+
};
105+
cp0_sdhci_pins: cp0-sdhi-pins-0 {
106+
marvell,pins = "mpp56", "mpp57", "mpp58",
107+
"mpp59", "mpp60", "mpp61";
108+
marvell,function = "sdio";
109+
};
110+
cp0_spi0_pins: cp0-spi-pins-0 {
111+
marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
112+
marvell,function = "spi1";
113+
};
114+
};
115+
};
116+
117+
&cp0_i2c0 {
118+
pinctrl-names = "default";
119+
pinctrl-0 = <&cp0_i2c0_pins>;
120+
status = "okay";
121+
clock-frequency = <100000>;
122+
expander0: mcp23x17@20 {
123+
compatible = "microchip,mcp23017";
124+
gpio-controller;
125+
#gpio-cells = <2>;
126+
reg = <0x20>;
127+
status = "okay";
128+
};
129+
};
130+
131+
&cp0_i2c1 {
132+
pinctrl-names = "default";
133+
pinctrl-0 = <&cp0_i2c1_pins>;
134+
clock-frequency = <100000>;
135+
status = "okay";
136+
};
137+
138+
139+
&cp0_sdhci0 {
140+
pinctrl-names = "default";
141+
pinctrl-0 = <&cp0_sdhci_pins
142+
&cp0_sdhci_cd_pins_crb>;
143+
bus-width = <4>;
144+
cd-gpios = <&cp0_gpio2 23 GPIO_ACTIVE_HIGH>;
145+
vqmmc-supply = <&cp0_reg_sd_vccq>;
146+
vmmc-supply = <&cp0_reg_sd_vcc>;
147+
status = "okay";
148+
};
149+
150+
&cp0_spi1 {
151+
pinctrl-names = "default";
152+
pinctrl-0 = <&cp0_spi0_pins>;
153+
reg = <0x700680 0x50>, /* control */
154+
<0x2000000 0x1000000>; /* CS0 */
155+
status = "okay";
156+
157+
spi-flash@0 {
158+
#address-cells = <0x1>;
159+
#size-cells = <0x1>;
160+
compatible = "jedec,spi-nor";
161+
reg = <0x0>;
162+
/* On-board MUX does not allow higher frequencies */
163+
spi-max-frequency = <40000000>;
164+
165+
partitions {
166+
compatible = "fixed-partitions";
167+
#address-cells = <1>;
168+
#size-cells = <1>;
169+
170+
partition@0 {
171+
label = "U-Boot";
172+
reg = <0x0 0x200000>;
173+
};
174+
175+
partition@400000 {
176+
label = "Filesystem";
177+
reg = <0x200000 0xe00000>;
178+
};
179+
};
180+
};
181+
};
182+
183+
&cp0_mdio {
184+
status = "okay";
185+
phy0: ethernet-phy@0 {
186+
reg = <0>;
187+
};
188+
};
189+
190+
&cp0_xmdio {
191+
status = "okay";
192+
nbaset_phy0: ethernet-phy@0 {
193+
compatible = "ethernet-phy-ieee802.3-c45";
194+
reg = <0>;
195+
};
196+
};
197+
198+
&cp0_ethernet {
199+
status = "okay";
200+
};
201+
202+
&cp0_eth0 {
203+
/* This port is connected to 88E6393X switch */
204+
status = "okay";
205+
phy-mode = "10gbase-r";
206+
managed = "in-band-status";
207+
phys = <&cp0_comphy4 0>;
208+
};
209+
210+
&cp0_eth1 {
211+
status = "okay";
212+
phy = <&phy0>;
213+
phy-mode = "rgmii-id";
214+
};
215+
216+
&cp0_eth2 {
217+
/* This port uses "2500base-t" phy-mode */
218+
status = "disabled";
219+
phy = <&nbaset_phy0>;
220+
phys = <&cp0_comphy5 2>;
221+
};
222+

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