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lucasdemarchilucasdemarchi
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drm/i915/gt: replace IS_GEN and friends with GRAPHICS_VER
This was done by the following semantic patch: @@ expression i915; @@ - INTEL_GEN(i915) + GRAPHICS_VER(i915) @@ expression i915; expression E; @@ - INTEL_GEN(i915) >= E + GRAPHICS_VER(i915) >= E @@ expression dev_priv; expression E; @@ - !IS_GEN(dev_priv, E) + GRAPHICS_VER(dev_priv) != E @@ expression dev_priv; expression E; @@ - IS_GEN(dev_priv, E) + GRAPHICS_VER(dev_priv) == E @@ expression dev_priv; expression from, until; @@ - IS_GEN_RANGE(dev_priv, from, until) + IS_GRAPHICS_VER(dev_priv, from, until) @def@ expression E; identifier id =~ "^gen$"; @@ - id = GRAPHICS_VER(E) + ver = GRAPHICS_VER(E) @@ identifier def.id; @@ - id + ver It also takes care of renaming the variable we assign to GRAPHICS_VER() so to use "ver" rather than "gen". Signed-off-by: Lucas De Marchi <[email protected]> Reviewed-by: Matt Roper <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
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+321
-320
lines changed

‎drivers/gpu/drm/i915/gt/debugfs_gt_pm.c

Lines changed: 19 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -85,22 +85,22 @@ static int gen6_drpc(struct seq_file *m)
8585
gt_core_status = intel_uncore_read_fw(uncore, GEN6_GT_CORE_STATUS);
8686

8787
rcctl1 = intel_uncore_read(uncore, GEN6_RC_CONTROL);
88-
if (INTEL_GEN(i915) >= 9) {
88+
if (GRAPHICS_VER(i915) >= 9) {
8989
gen9_powergate_enable =
9090
intel_uncore_read(uncore, GEN9_PG_ENABLE);
9191
gen9_powergate_status =
9292
intel_uncore_read(uncore, GEN9_PWRGT_DOMAIN_STATUS);
9393
}
9494

95-
if (INTEL_GEN(i915) <= 7)
95+
if (GRAPHICS_VER(i915) <= 7)
9696
sandybridge_pcode_read(i915, GEN6_PCODE_READ_RC6VIDS,
9797
&rc6vids, NULL);
9898

9999
seq_printf(m, "RC1e Enabled: %s\n",
100100
yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
101101
seq_printf(m, "RC6 Enabled: %s\n",
102102
yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
103-
if (INTEL_GEN(i915) >= 9) {
103+
if (GRAPHICS_VER(i915) >= 9) {
104104
seq_printf(m, "Render Well Gating Enabled: %s\n",
105105
yesno(gen9_powergate_enable & GEN9_RENDER_PG_ENABLE));
106106
seq_printf(m, "Media Well Gating Enabled: %s\n",
@@ -134,7 +134,7 @@ static int gen6_drpc(struct seq_file *m)
134134

135135
seq_printf(m, "Core Power Down: %s\n",
136136
yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
137-
if (INTEL_GEN(i915) >= 9) {
137+
if (GRAPHICS_VER(i915) >= 9) {
138138
seq_printf(m, "Render Power Well: %s\n",
139139
(gen9_powergate_status &
140140
GEN9_PWRGT_RENDER_STATUS_MASK) ? "Up" : "Down");
@@ -150,7 +150,7 @@ static int gen6_drpc(struct seq_file *m)
150150
print_rc6_res(m, "RC6+ residency since boot:", GEN6_GT_GFX_RC6p);
151151
print_rc6_res(m, "RC6++ residency since boot:", GEN6_GT_GFX_RC6pp);
152152

153-
if (INTEL_GEN(i915) <= 7) {
153+
if (GRAPHICS_VER(i915) <= 7) {
154154
seq_printf(m, "RC6 voltage: %dmV\n",
155155
GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
156156
seq_printf(m, "RC6+ voltage: %dmV\n",
@@ -250,7 +250,7 @@ static int frequency_show(struct seq_file *m, void *unused)
250250

251251
wakeref = intel_runtime_pm_get(uncore->rpm);
252252

253-
if (IS_GEN(i915, 5)) {
253+
if (GRAPHICS_VER(i915) == 5) {
254254
u16 rgvswctl = intel_uncore_read16(uncore, MEMSWCTL);
255255
u16 rgvstat = intel_uncore_read16(uncore, MEMSTAT_ILK);
256256

@@ -296,7 +296,7 @@ static int frequency_show(struct seq_file *m, void *unused)
296296

297297
seq_printf(m, "efficient (RPe) frequency: %d MHz\n",
298298
intel_gpu_freq(rps, rps->efficient_freq));
299-
} else if (INTEL_GEN(i915) >= 6) {
299+
} else if (GRAPHICS_VER(i915) >= 6) {
300300
u32 rp_state_limits;
301301
u32 gt_perf_status;
302302
u32 rp_state_cap;
@@ -321,7 +321,7 @@ static int frequency_show(struct seq_file *m, void *unused)
321321
intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
322322

323323
reqf = intel_uncore_read(uncore, GEN6_RPNSWREQ);
324-
if (INTEL_GEN(i915) >= 9) {
324+
if (GRAPHICS_VER(i915) >= 9) {
325325
reqf >>= 23;
326326
} else {
327327
reqf &= ~GEN6_TURBO_DISABLE;
@@ -354,7 +354,7 @@ static int frequency_show(struct seq_file *m, void *unused)
354354

355355
intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
356356

357-
if (INTEL_GEN(i915) >= 11) {
357+
if (GRAPHICS_VER(i915) >= 11) {
358358
pm_ier = intel_uncore_read(uncore, GEN11_GPM_WGBOXPERF_INTR_ENABLE);
359359
pm_imr = intel_uncore_read(uncore, GEN11_GPM_WGBOXPERF_INTR_MASK);
360360
/*
@@ -363,7 +363,7 @@ static int frequency_show(struct seq_file *m, void *unused)
363363
*/
364364
pm_isr = 0;
365365
pm_iir = 0;
366-
} else if (INTEL_GEN(i915) >= 8) {
366+
} else if (GRAPHICS_VER(i915) >= 8) {
367367
pm_ier = intel_uncore_read(uncore, GEN8_GT_IER(2));
368368
pm_imr = intel_uncore_read(uncore, GEN8_GT_IMR(2));
369369
pm_isr = intel_uncore_read(uncore, GEN8_GT_ISR(2));
@@ -386,14 +386,14 @@ static int frequency_show(struct seq_file *m, void *unused)
386386

387387
seq_printf(m, "PM IER=0x%08x IMR=0x%08x, MASK=0x%08x\n",
388388
pm_ier, pm_imr, pm_mask);
389-
if (INTEL_GEN(i915) <= 10)
389+
if (GRAPHICS_VER(i915) <= 10)
390390
seq_printf(m, "PM ISR=0x%08x IIR=0x%08x\n",
391391
pm_isr, pm_iir);
392392
seq_printf(m, "pm_intrmsk_mbz: 0x%08x\n",
393393
rps->pm_intrmsk_mbz);
394394
seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
395395
seq_printf(m, "Render p-state ratio: %d\n",
396-
(gt_perf_status & (INTEL_GEN(i915) >= 9 ? 0x1ff00 : 0xff00)) >> 8);
396+
(gt_perf_status & (GRAPHICS_VER(i915) >= 9 ? 0x1ff00 : 0xff00)) >> 8);
397397
seq_printf(m, "Render p-state VID: %d\n",
398398
gt_perf_status & 0xff);
399399
seq_printf(m, "Render p-state limit: %d\n",
@@ -437,20 +437,20 @@ static int frequency_show(struct seq_file *m, void *unused)
437437
max_freq = (IS_GEN9_LP(i915) ? rp_state_cap >> 0 :
438438
rp_state_cap >> 16) & 0xff;
439439
max_freq *= (IS_GEN9_BC(i915) ||
440-
INTEL_GEN(i915) >= 10 ? GEN9_FREQ_SCALER : 1);
440+
GRAPHICS_VER(i915) >= 10 ? GEN9_FREQ_SCALER : 1);
441441
seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
442442
intel_gpu_freq(rps, max_freq));
443443

444444
max_freq = (rp_state_cap & 0xff00) >> 8;
445445
max_freq *= (IS_GEN9_BC(i915) ||
446-
INTEL_GEN(i915) >= 10 ? GEN9_FREQ_SCALER : 1);
446+
GRAPHICS_VER(i915) >= 10 ? GEN9_FREQ_SCALER : 1);
447447
seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
448448
intel_gpu_freq(rps, max_freq));
449449

450450
max_freq = (IS_GEN9_LP(i915) ? rp_state_cap >> 16 :
451451
rp_state_cap >> 0) & 0xff;
452452
max_freq *= (IS_GEN9_BC(i915) ||
453-
INTEL_GEN(i915) >= 10 ? GEN9_FREQ_SCALER : 1);
453+
GRAPHICS_VER(i915) >= 10 ? GEN9_FREQ_SCALER : 1);
454454
seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
455455
intel_gpu_freq(rps, max_freq));
456456
seq_printf(m, "Max overclocked frequency: %dMHz\n",
@@ -488,7 +488,7 @@ static int llc_show(struct seq_file *m, void *data)
488488
{
489489
struct intel_gt *gt = m->private;
490490
struct drm_i915_private *i915 = gt->i915;
491-
const bool edram = INTEL_GEN(i915) > 8;
491+
const bool edram = GRAPHICS_VER(i915) > 8;
492492
struct intel_rps *rps = &gt->rps;
493493
unsigned int max_gpu_freq, min_gpu_freq;
494494
intel_wakeref_t wakeref;
@@ -500,7 +500,7 @@ static int llc_show(struct seq_file *m, void *data)
500500

501501
min_gpu_freq = rps->min_freq;
502502
max_gpu_freq = rps->max_freq;
503-
if (IS_GEN9_BC(i915) || INTEL_GEN(i915) >= 10) {
503+
if (IS_GEN9_BC(i915) || GRAPHICS_VER(i915) >= 10) {
504504
/* Convert GT frequency to 50 HZ units */
505505
min_gpu_freq /= GEN9_FREQ_SCALER;
506506
max_gpu_freq /= GEN9_FREQ_SCALER;
@@ -518,7 +518,7 @@ static int llc_show(struct seq_file *m, void *data)
518518
intel_gpu_freq(rps,
519519
(gpu_freq *
520520
(IS_GEN9_BC(i915) ||
521-
INTEL_GEN(i915) >= 10 ?
521+
GRAPHICS_VER(i915) >= 10 ?
522522
GEN9_FREQ_SCALER : 1))),
523523
((ia_freq >> 0) & 0xff) * 100,
524524
((ia_freq >> 8) & 0xff) * 100);
@@ -580,7 +580,7 @@ static int rps_boost_show(struct seq_file *m, void *data)
580580

581581
seq_printf(m, "Wait boosts: %d\n", READ_ONCE(rps->boosts));
582582

583-
if (INTEL_GEN(i915) >= 6 && intel_rps_is_active(rps)) {
583+
if (GRAPHICS_VER(i915) >= 6 && intel_rps_is_active(rps)) {
584584
struct intel_uncore *uncore = gt->uncore;
585585
u32 rpup, rpupei;
586586
u32 rpdown, rpdownei;

‎drivers/gpu/drm/i915/gt/gen2_engine_cs.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -74,7 +74,7 @@ int gen4_emit_flush_rcs(struct i915_request *rq, u32 mode)
7474
cmd = MI_FLUSH;
7575
if (mode & EMIT_INVALIDATE) {
7676
cmd |= MI_EXE_FLUSH;
77-
if (IS_G4X(rq->engine->i915) || IS_GEN(rq->engine->i915, 5))
77+
if (IS_G4X(rq->engine->i915) || GRAPHICS_VER(rq->engine->i915) == 5)
7878
cmd |= MI_INVALIDATE_ISP;
7979
}
8080

‎drivers/gpu/drm/i915/gt/gen8_engine_cs.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -38,7 +38,7 @@ int gen8_emit_flush_rcs(struct i915_request *rq, u32 mode)
3838
* On GEN9: before VF_CACHE_INVALIDATE we need to emit a NULL
3939
* pipe control.
4040
*/
41-
if (IS_GEN(rq->engine->i915, 9))
41+
if (GRAPHICS_VER(rq->engine->i915) == 9)
4242
vf_flush_wa = true;
4343

4444
/* WaForGAMHang:kbl */

‎drivers/gpu/drm/i915/gt/gen8_ppgtt.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -709,7 +709,7 @@ struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt)
709709
*
710710
* Gen12 has inherited the same read-only fault issue from gen11.
711711
*/
712-
ppgtt->vm.has_read_only = !IS_GEN_RANGE(gt->i915, 11, 12);
712+
ppgtt->vm.has_read_only = !IS_GRAPHICS_VER(gt->i915, 11, 12);
713713

714714
if (HAS_LMEM(gt->i915))
715715
ppgtt->vm.alloc_pt_dma = alloc_pt_lmem;

‎drivers/gpu/drm/i915/gt/intel_context_sseu.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -76,7 +76,7 @@ intel_context_reconfigure_sseu(struct intel_context *ce,
7676
{
7777
int ret;
7878

79-
GEM_BUG_ON(INTEL_GEN(ce->engine->i915) < 8);
79+
GEM_BUG_ON(GRAPHICS_VER(ce->engine->i915) < 8);
8080

8181
ret = intel_context_lock_pinned(ce);
8282
if (ret)

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