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Bindu Ramamurthyalexdeucher
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drm/amd/display: Populate dtbclk entries for dcn3.02/3.03
[Why] Populate dtbclk values from bwparams for dcn302, dcn303. [How] dtbclk values are fetched from bandwidthparams for all DPM levels and for DPM levels where smu returns 0, previous level values are reported. Reviewed-by: Roman Li <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Bindu Ramamurthy <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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lines changed

2 files changed

+10
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drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1398,7 +1398,11 @@ void dcn302_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_param
13981398
dcn3_02_soc.clock_limits[i].dispclk_mhz = max_dispclk_mhz;
13991399
dcn3_02_soc.clock_limits[i].dppclk_mhz = max_dppclk_mhz;
14001400
dcn3_02_soc.clock_limits[i].phyclk_mhz = max_phyclk_mhz;
1401-
dcn3_02_soc.clock_limits[i].dtbclk_mhz = dcn3_02_soc.clock_limits[0].dtbclk_mhz;
1401+
/* Populate from bw_params for DTBCLK, SOCCLK */
1402+
if (!bw_params->clk_table.entries[i].dtbclk_mhz && i > 0)
1403+
dcn3_02_soc.clock_limits[i].dtbclk_mhz = dcn3_02_soc.clock_limits[i-1].dtbclk_mhz;
1404+
else
1405+
dcn3_02_soc.clock_limits[i].dtbclk_mhz = bw_params->clk_table.entries[i].dtbclk_mhz;
14021406
if (!bw_params->clk_table.entries[i].socclk_mhz && i > 0)
14031407
dcn3_02_soc.clock_limits[i].socclk_mhz = dcn3_02_soc.clock_limits[i-1].socclk_mhz;
14041408
else

drivers/gpu/drm/amd/display/dc/dcn303/dcn303_resource.c

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1326,7 +1326,11 @@ void dcn303_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_param
13261326
dcn3_03_soc.clock_limits[i].dispclk_mhz = max_dispclk_mhz;
13271327
dcn3_03_soc.clock_limits[i].dppclk_mhz = max_dppclk_mhz;
13281328
dcn3_03_soc.clock_limits[i].phyclk_mhz = max_phyclk_mhz;
1329-
dcn3_03_soc.clock_limits[i].dtbclk_mhz = dcn3_03_soc.clock_limits[0].dtbclk_mhz;
1329+
/* Populate from bw_params for DTBCLK, SOCCLK */
1330+
if (!bw_params->clk_table.entries[i].dtbclk_mhz && i > 0)
1331+
dcn3_03_soc.clock_limits[i].dtbclk_mhz = dcn3_03_soc.clock_limits[i-1].dtbclk_mhz;
1332+
else
1333+
dcn3_03_soc.clock_limits[i].dtbclk_mhz = bw_params->clk_table.entries[i].dtbclk_mhz;
13301334
if (!bw_params->clk_table.entries[i].socclk_mhz && i > 0)
13311335
dcn3_03_soc.clock_limits[i].socclk_mhz = dcn3_03_soc.clock_limits[i-1].socclk_mhz;
13321336
else

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