Skip to content

Commit d62ad76

Browse files
wenliangwubroonie
wenliangwu
authored and
broonie
committed
ASoC: mediatek: mt8195: support audsys clock control
This patch adds mt8195 audio cg control. Audio clock gates are registered to CCF for reference count and clock parent management. Signed-off-by: Trevor Wu <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Mark Brown <[email protected]>
1 parent cab2b9e commit d62ad76

File tree

3 files changed

+322
-0
lines changed

3 files changed

+322
-0
lines changed

‎sound/soc/mediatek/mt8195/mt8195-audsys-clk.c

Lines changed: 214 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,214 @@
1+
// SPDX-License-Identifier: GPL-2.0
2+
/*
3+
* mt8195-audsys-clk.h -- Mediatek 8195 audsys clock control
4+
*
5+
* Copyright (c) 2021 MediaTek Inc.
6+
* Author: Trevor Wu <[email protected]>
7+
*/
8+
9+
#include <linux/clk.h>
10+
#include <linux/clk-provider.h>
11+
#include <linux/clkdev.h>
12+
#include "mt8195-afe-common.h"
13+
#include "mt8195-audsys-clk.h"
14+
#include "mt8195-audsys-clkid.h"
15+
#include "mt8195-reg.h"
16+
17+
struct afe_gate {
18+
int id;
19+
const char *name;
20+
const char *parent_name;
21+
int reg;
22+
u8 bit;
23+
const struct clk_ops *ops;
24+
unsigned long flags;
25+
u8 cg_flags;
26+
};
27+
28+
#define GATE_AFE_FLAGS(_id, _name, _parent, _reg, _bit, _flags, _cgflags) {\
29+
.id = _id, \
30+
.name = _name, \
31+
.parent_name = _parent, \
32+
.reg = _reg, \
33+
.bit = _bit, \
34+
.flags = _flags, \
35+
.cg_flags = _cgflags, \
36+
}
37+
38+
#define GATE_AFE(_id, _name, _parent, _reg, _bit) \
39+
GATE_AFE_FLAGS(_id, _name, _parent, _reg, _bit, \
40+
CLK_SET_RATE_PARENT, CLK_GATE_SET_TO_DISABLE)
41+
42+
#define GATE_AUD0(_id, _name, _parent, _bit) \
43+
GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON0, _bit)
44+
45+
#define GATE_AUD1(_id, _name, _parent, _bit) \
46+
GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON1, _bit)
47+
48+
#define GATE_AUD3(_id, _name, _parent, _bit) \
49+
GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON3, _bit)
50+
51+
#define GATE_AUD4(_id, _name, _parent, _bit) \
52+
GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON4, _bit)
53+
54+
#define GATE_AUD5(_id, _name, _parent, _bit) \
55+
GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON5, _bit)
56+
57+
#define GATE_AUD6(_id, _name, _parent, _bit) \
58+
GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON6, _bit)
59+
60+
static const struct afe_gate aud_clks[CLK_AUD_NR_CLK] = {
61+
/* AUD0 */
62+
GATE_AUD0(CLK_AUD_AFE, "aud_afe", "a1sys_hp_sel", 2),
63+
GATE_AUD0(CLK_AUD_LRCK_CNT, "aud_lrck_cnt", "a1sys_hp_sel", 4),
64+
GATE_AUD0(CLK_AUD_SPDIFIN_TUNER_APLL, "aud_spdifin_tuner_apll", "apll4_sel", 10),
65+
GATE_AUD0(CLK_AUD_SPDIFIN_TUNER_DBG, "aud_spdifin_tuner_dbg", "apll4_sel", 11),
66+
GATE_AUD0(CLK_AUD_UL_TML, "aud_ul_tml", "a1sys_hp_sel", 18),
67+
GATE_AUD0(CLK_AUD_APLL1_TUNER, "aud_apll1_tuner", "apll1_sel", 19),
68+
GATE_AUD0(CLK_AUD_APLL2_TUNER, "aud_apll2_tuner", "apll2_sel", 20),
69+
GATE_AUD0(CLK_AUD_TOP0_SPDF, "aud_top0_spdf", "aud_iec_sel", 21),
70+
GATE_AUD0(CLK_AUD_APLL, "aud_apll", "apll1_sel", 23),
71+
GATE_AUD0(CLK_AUD_APLL2, "aud_apll2", "apll2_sel", 24),
72+
GATE_AUD0(CLK_AUD_DAC, "aud_dac", "a1sys_hp_sel", 25),
73+
GATE_AUD0(CLK_AUD_DAC_PREDIS, "aud_dac_predis", "a1sys_hp_sel", 26),
74+
GATE_AUD0(CLK_AUD_TML, "aud_tml", "a1sys_hp_sel", 27),
75+
GATE_AUD0(CLK_AUD_ADC, "aud_adc", "a1sys_hp_sel", 28),
76+
GATE_AUD0(CLK_AUD_DAC_HIRES, "aud_dac_hires", "audio_h_sel", 31),
77+
78+
/* AUD1 */
79+
GATE_AUD1(CLK_AUD_A1SYS_HP, "aud_a1sys_hp", "a1sys_hp_sel", 2),
80+
GATE_AUD1(CLK_AUD_AFE_DMIC1, "aud_afe_dmic1", "a1sys_hp_sel", 10),
81+
GATE_AUD1(CLK_AUD_AFE_DMIC2, "aud_afe_dmic2", "a1sys_hp_sel", 11),
82+
GATE_AUD1(CLK_AUD_AFE_DMIC3, "aud_afe_dmic3", "a1sys_hp_sel", 12),
83+
GATE_AUD1(CLK_AUD_AFE_DMIC4, "aud_afe_dmic4", "a1sys_hp_sel", 13),
84+
GATE_AUD1(CLK_AUD_AFE_26M_DMIC_TM, "aud_afe_26m_dmic_tm", "a1sys_hp_sel", 14),
85+
GATE_AUD1(CLK_AUD_UL_TML_HIRES, "aud_ul_tml_hires", "audio_h_sel", 16),
86+
GATE_AUD1(CLK_AUD_ADC_HIRES, "aud_adc_hires", "audio_h_sel", 17),
87+
GATE_AUD1(CLK_AUD_ADDA6_ADC, "aud_adda6_adc", "a1sys_hp_sel", 18),
88+
GATE_AUD1(CLK_AUD_ADDA6_ADC_HIRES, "aud_adda6_adc_hires", "audio_h_sel", 19),
89+
90+
/* AUD3 */
91+
GATE_AUD3(CLK_AUD_LINEIN_TUNER, "aud_linein_tuner", "apll5_sel", 5),
92+
GATE_AUD3(CLK_AUD_EARC_TUNER, "aud_earc_tuner", "apll3_sel", 7),
93+
94+
/* AUD4 */
95+
GATE_AUD4(CLK_AUD_I2SIN, "aud_i2sin", "a1sys_hp_sel", 0),
96+
GATE_AUD4(CLK_AUD_TDM_IN, "aud_tdm_in", "a1sys_hp_sel", 1),
97+
GATE_AUD4(CLK_AUD_I2S_OUT, "aud_i2s_out", "a1sys_hp_sel", 6),
98+
GATE_AUD4(CLK_AUD_TDM_OUT, "aud_tdm_out", "a1sys_hp_sel", 7),
99+
GATE_AUD4(CLK_AUD_HDMI_OUT, "aud_hdmi_out", "a1sys_hp_sel", 8),
100+
GATE_AUD4(CLK_AUD_ASRC11, "aud_asrc11", "a1sys_hp_sel", 16),
101+
GATE_AUD4(CLK_AUD_ASRC12, "aud_asrc12", "a1sys_hp_sel", 17),
102+
GATE_AUD4(CLK_AUD_MULTI_IN, "aud_multi_in", "mphone_slave_b", 19),
103+
GATE_AUD4(CLK_AUD_INTDIR, "aud_intdir", "intdir_sel", 20),
104+
GATE_AUD4(CLK_AUD_A1SYS, "aud_a1sys", "a1sys_hp_sel", 21),
105+
GATE_AUD4(CLK_AUD_A2SYS, "aud_a2sys", "a2sys_sel", 22),
106+
GATE_AUD4(CLK_AUD_PCMIF, "aud_pcmif", "a1sys_hp_sel", 24),
107+
GATE_AUD4(CLK_AUD_A3SYS, "aud_a3sys", "a3sys_sel", 30),
108+
GATE_AUD4(CLK_AUD_A4SYS, "aud_a4sys", "a4sys_sel", 31),
109+
110+
/* AUD5 */
111+
GATE_AUD5(CLK_AUD_MEMIF_UL1, "aud_memif_ul1", "a1sys_hp_sel", 0),
112+
GATE_AUD5(CLK_AUD_MEMIF_UL2, "aud_memif_ul2", "a1sys_hp_sel", 1),
113+
GATE_AUD5(CLK_AUD_MEMIF_UL3, "aud_memif_ul3", "a1sys_hp_sel", 2),
114+
GATE_AUD5(CLK_AUD_MEMIF_UL4, "aud_memif_ul4", "a1sys_hp_sel", 3),
115+
GATE_AUD5(CLK_AUD_MEMIF_UL5, "aud_memif_ul5", "a1sys_hp_sel", 4),
116+
GATE_AUD5(CLK_AUD_MEMIF_UL6, "aud_memif_ul6", "a1sys_hp_sel", 5),
117+
GATE_AUD5(CLK_AUD_MEMIF_UL8, "aud_memif_ul8", "a1sys_hp_sel", 7),
118+
GATE_AUD5(CLK_AUD_MEMIF_UL9, "aud_memif_ul9", "a1sys_hp_sel", 8),
119+
GATE_AUD5(CLK_AUD_MEMIF_UL10, "aud_memif_ul10", "a1sys_hp_sel", 9),
120+
GATE_AUD5(CLK_AUD_MEMIF_DL2, "aud_memif_dl2", "a1sys_hp_sel", 18),
121+
GATE_AUD5(CLK_AUD_MEMIF_DL3, "aud_memif_dl3", "a1sys_hp_sel", 19),
122+
GATE_AUD5(CLK_AUD_MEMIF_DL6, "aud_memif_dl6", "a1sys_hp_sel", 22),
123+
GATE_AUD5(CLK_AUD_MEMIF_DL7, "aud_memif_dl7", "a1sys_hp_sel", 23),
124+
GATE_AUD5(CLK_AUD_MEMIF_DL8, "aud_memif_dl8", "a1sys_hp_sel", 24),
125+
GATE_AUD5(CLK_AUD_MEMIF_DL10, "aud_memif_dl10", "a1sys_hp_sel", 26),
126+
GATE_AUD5(CLK_AUD_MEMIF_DL11, "aud_memif_dl11", "a1sys_hp_sel", 27),
127+
128+
/* AUD6 */
129+
GATE_AUD6(CLK_AUD_GASRC0, "aud_gasrc0", "asm_h_sel", 0),
130+
GATE_AUD6(CLK_AUD_GASRC1, "aud_gasrc1", "asm_h_sel", 1),
131+
GATE_AUD6(CLK_AUD_GASRC2, "aud_gasrc2", "asm_h_sel", 2),
132+
GATE_AUD6(CLK_AUD_GASRC3, "aud_gasrc3", "asm_h_sel", 3),
133+
GATE_AUD6(CLK_AUD_GASRC4, "aud_gasrc4", "asm_h_sel", 4),
134+
GATE_AUD6(CLK_AUD_GASRC5, "aud_gasrc5", "asm_h_sel", 5),
135+
GATE_AUD6(CLK_AUD_GASRC6, "aud_gasrc6", "asm_h_sel", 6),
136+
GATE_AUD6(CLK_AUD_GASRC7, "aud_gasrc7", "asm_h_sel", 7),
137+
GATE_AUD6(CLK_AUD_GASRC8, "aud_gasrc8", "asm_h_sel", 8),
138+
GATE_AUD6(CLK_AUD_GASRC9, "aud_gasrc9", "asm_h_sel", 9),
139+
GATE_AUD6(CLK_AUD_GASRC10, "aud_gasrc10", "asm_h_sel", 10),
140+
GATE_AUD6(CLK_AUD_GASRC11, "aud_gasrc11", "asm_h_sel", 11),
141+
GATE_AUD6(CLK_AUD_GASRC12, "aud_gasrc12", "asm_h_sel", 12),
142+
GATE_AUD6(CLK_AUD_GASRC13, "aud_gasrc13", "asm_h_sel", 13),
143+
GATE_AUD6(CLK_AUD_GASRC14, "aud_gasrc14", "asm_h_sel", 14),
144+
GATE_AUD6(CLK_AUD_GASRC15, "aud_gasrc15", "asm_h_sel", 15),
145+
GATE_AUD6(CLK_AUD_GASRC16, "aud_gasrc16", "asm_h_sel", 16),
146+
GATE_AUD6(CLK_AUD_GASRC17, "aud_gasrc17", "asm_h_sel", 17),
147+
GATE_AUD6(CLK_AUD_GASRC18, "aud_gasrc18", "asm_h_sel", 18),
148+
GATE_AUD6(CLK_AUD_GASRC19, "aud_gasrc19", "asm_h_sel", 19),
149+
};
150+
151+
int mt8195_audsys_clk_register(struct mtk_base_afe *afe)
152+
{
153+
struct mt8195_afe_private *afe_priv = afe->platform_priv;
154+
struct clk *clk;
155+
struct clk_lookup *cl;
156+
int i;
157+
158+
afe_priv->lookup = devm_kcalloc(afe->dev, CLK_AUD_NR_CLK,
159+
sizeof(*afe_priv->lookup),
160+
GFP_KERNEL);
161+
162+
if (!afe_priv->lookup)
163+
return -ENOMEM;
164+
165+
for (i = 0; i < ARRAY_SIZE(aud_clks); i++) {
166+
const struct afe_gate *gate = &aud_clks[i];
167+
168+
clk = clk_register_gate(afe->dev, gate->name, gate->parent_name,
169+
gate->flags, afe->base_addr + gate->reg,
170+
gate->bit, gate->cg_flags, NULL);
171+
172+
if (IS_ERR(clk)) {
173+
dev_err(afe->dev, "Failed to register clk %s: %ld\n",
174+
gate->name, PTR_ERR(clk));
175+
continue;
176+
}
177+
178+
/* add clk_lookup for devm_clk_get(SND_SOC_DAPM_CLOCK_SUPPLY) */
179+
cl = kzalloc(sizeof(*cl), GFP_KERNEL);
180+
if (!cl)
181+
return -ENOMEM;
182+
183+
cl->clk = clk;
184+
cl->con_id = gate->name;
185+
cl->dev_id = dev_name(afe->dev);
186+
clkdev_add(cl);
187+
188+
afe_priv->lookup[i] = cl;
189+
}
190+
191+
return 0;
192+
}
193+
194+
void mt8195_audsys_clk_unregister(struct mtk_base_afe *afe)
195+
{
196+
struct mt8195_afe_private *afe_priv = afe->platform_priv;
197+
struct clk *clk;
198+
struct clk_lookup *cl;
199+
int i;
200+
201+
if (!afe_priv)
202+
return;
203+
204+
for (i = 0; i < CLK_AUD_NR_CLK; i++) {
205+
cl = afe_priv->lookup[i];
206+
if (!cl)
207+
continue;
208+
209+
clk = cl->clk;
210+
clk_unregister_gate(clk);
211+
212+
clkdev_drop(cl);
213+
}
214+
}

‎sound/soc/mediatek/mt8195/mt8195-audsys-clk.h

Lines changed: 15 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,15 @@
1+
/* SPDX-License-Identifier: GPL-2.0 */
2+
/*
3+
* mt8195-audsys-clk.h -- Mediatek 8195 audsys clock definition
4+
*
5+
* Copyright (c) 2021 MediaTek Inc.
6+
* Author: Trevor Wu <[email protected]>
7+
*/
8+
9+
#ifndef _MT8195_AUDSYS_CLK_H_
10+
#define _MT8195_AUDSYS_CLK_H_
11+
12+
int mt8195_audsys_clk_register(struct mtk_base_afe *afe);
13+
void mt8195_audsys_clk_unregister(struct mtk_base_afe *afe);
14+
15+
#endif

‎sound/soc/mediatek/mt8195/mt8195-audsys-clkid.h

Lines changed: 93 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,93 @@
1+
/* SPDX-License-Identifier: GPL-2.0 */
2+
/*
3+
* mt8195-audsys-clkid.h -- Mediatek 8195 audsys clock id definition
4+
*
5+
* Copyright (c) 2021 MediaTek Inc.
6+
* Author: Trevor Wu <[email protected]>
7+
*/
8+
9+
#ifndef _MT8195_AUDSYS_CLKID_H_
10+
#define _MT8195_AUDSYS_CLKID_H_
11+
12+
enum{
13+
CLK_AUD_AFE,
14+
CLK_AUD_LRCK_CNT,
15+
CLK_AUD_SPDIFIN_TUNER_APLL,
16+
CLK_AUD_SPDIFIN_TUNER_DBG,
17+
CLK_AUD_UL_TML,
18+
CLK_AUD_APLL1_TUNER,
19+
CLK_AUD_APLL2_TUNER,
20+
CLK_AUD_TOP0_SPDF,
21+
CLK_AUD_APLL,
22+
CLK_AUD_APLL2,
23+
CLK_AUD_DAC,
24+
CLK_AUD_DAC_PREDIS,
25+
CLK_AUD_TML,
26+
CLK_AUD_ADC,
27+
CLK_AUD_DAC_HIRES,
28+
CLK_AUD_A1SYS_HP,
29+
CLK_AUD_AFE_DMIC1,
30+
CLK_AUD_AFE_DMIC2,
31+
CLK_AUD_AFE_DMIC3,
32+
CLK_AUD_AFE_DMIC4,
33+
CLK_AUD_AFE_26M_DMIC_TM,
34+
CLK_AUD_UL_TML_HIRES,
35+
CLK_AUD_ADC_HIRES,
36+
CLK_AUD_ADDA6_ADC,
37+
CLK_AUD_ADDA6_ADC_HIRES,
38+
CLK_AUD_LINEIN_TUNER,
39+
CLK_AUD_EARC_TUNER,
40+
CLK_AUD_I2SIN,
41+
CLK_AUD_TDM_IN,
42+
CLK_AUD_I2S_OUT,
43+
CLK_AUD_TDM_OUT,
44+
CLK_AUD_HDMI_OUT,
45+
CLK_AUD_ASRC11,
46+
CLK_AUD_ASRC12,
47+
CLK_AUD_MULTI_IN,
48+
CLK_AUD_INTDIR,
49+
CLK_AUD_A1SYS,
50+
CLK_AUD_A2SYS,
51+
CLK_AUD_PCMIF,
52+
CLK_AUD_A3SYS,
53+
CLK_AUD_A4SYS,
54+
CLK_AUD_MEMIF_UL1,
55+
CLK_AUD_MEMIF_UL2,
56+
CLK_AUD_MEMIF_UL3,
57+
CLK_AUD_MEMIF_UL4,
58+
CLK_AUD_MEMIF_UL5,
59+
CLK_AUD_MEMIF_UL6,
60+
CLK_AUD_MEMIF_UL8,
61+
CLK_AUD_MEMIF_UL9,
62+
CLK_AUD_MEMIF_UL10,
63+
CLK_AUD_MEMIF_DL2,
64+
CLK_AUD_MEMIF_DL3,
65+
CLK_AUD_MEMIF_DL6,
66+
CLK_AUD_MEMIF_DL7,
67+
CLK_AUD_MEMIF_DL8,
68+
CLK_AUD_MEMIF_DL10,
69+
CLK_AUD_MEMIF_DL11,
70+
CLK_AUD_GASRC0,
71+
CLK_AUD_GASRC1,
72+
CLK_AUD_GASRC2,
73+
CLK_AUD_GASRC3,
74+
CLK_AUD_GASRC4,
75+
CLK_AUD_GASRC5,
76+
CLK_AUD_GASRC6,
77+
CLK_AUD_GASRC7,
78+
CLK_AUD_GASRC8,
79+
CLK_AUD_GASRC9,
80+
CLK_AUD_GASRC10,
81+
CLK_AUD_GASRC11,
82+
CLK_AUD_GASRC12,
83+
CLK_AUD_GASRC13,
84+
CLK_AUD_GASRC14,
85+
CLK_AUD_GASRC15,
86+
CLK_AUD_GASRC16,
87+
CLK_AUD_GASRC17,
88+
CLK_AUD_GASRC18,
89+
CLK_AUD_GASRC19,
90+
CLK_AUD_NR_CLK,
91+
};
92+
93+
#endif

0 commit comments

Comments
 (0)