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Merge tag 'devicetree-fixes-for-5.14-1' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux
Pull devicetree fixes from Rob Herring: - Drop 'resets' as required on renesas,du - Moving of fixed string patterns for 'properties' instead of 'patternProperties' - Drop more redundant minItems/maxItems that we merged in the merge window - Indentation warning fix for sja1105 * tag 'devicetree-fixes-for-5.14-1' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: dt-bindings: display: renesas,du: Make resets optional on R-Car H1 dt-bindings: Move fixed string 'patternProperties' to 'properties' dt-bindings: More dropping redundant minItems/maxItems dt-bindings: net: dsa: sja1105: Fix indentation warnings
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‎Documentation/devicetree/bindings/clock/brcm,iproc-clocks.yaml

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@@ -50,7 +50,6 @@ properties:
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reg:
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minItems: 1
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maxItems: 3
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items:
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- description: base register
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- description: power register

‎Documentation/devicetree/bindings/display/renesas,du.yaml

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@@ -92,7 +92,6 @@ required:
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- reg
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- clocks
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- interrupts
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- resets
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- ports
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allOf:

‎Documentation/devicetree/bindings/hwmon/adt7475.yaml

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@@ -39,17 +39,7 @@ properties:
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reg:
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maxItems: 1
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patternProperties:
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"^adi,bypass-attenuator-in[0-4]$":
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description: |
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Configures bypassing the individual voltage input attenuator. If
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set to 1 the attenuator is bypassed if set to 0 the attenuator is
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not bypassed. If the property is absent then the attenuator
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retains it's configuration from the bios/bootloader.
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$ref: /schemas/types.yaml#/definitions/uint32
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enum: [0, 1]
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"^adi,pwm-active-state$":
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adi,pwm-active-state:
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description: |
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Integer array, represents the active state of the pwm outputs If set to 0
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the pwm uses a logic low output for 100% duty cycle. If set to 1 the pwm
@@ -61,6 +51,16 @@ patternProperties:
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enum: [0, 1]
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default: 1
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patternProperties:
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"^adi,bypass-attenuator-in[0-4]$":
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description: |
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Configures bypassing the individual voltage input attenuator. If
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set to 1 the attenuator is bypassed if set to 0 the attenuator is
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not bypassed. If the property is absent then the attenuator
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retains it's configuration from the bios/bootloader.
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$ref: /schemas/types.yaml#/definitions/uint32
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enum: [0, 1]
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required:
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- compatible
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- reg

‎Documentation/devicetree/bindings/iommu/rockchip,iommu.yaml

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@@ -28,14 +28,12 @@ properties:
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- description: configuration registers for MMU instance 0
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- description: configuration registers for MMU instance 1
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minItems: 1
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maxItems: 2
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interrupts:
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items:
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- description: interruption for MMU instance 0
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- description: interruption for MMU instance 1
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minItems: 1
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maxItems: 2
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clocks:
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items:

‎Documentation/devicetree/bindings/memory-controllers/arm,pl353-smc.yaml

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@@ -57,7 +57,6 @@ properties:
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ranges:
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minItems: 1
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maxItems: 3
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description: |
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Memory bus areas for interacting with the devices. Reflects
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the memory layout with four integer values following:

‎Documentation/devicetree/bindings/mtd/brcm,brcmnand.yaml

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@@ -84,15 +84,13 @@ properties:
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interrupts:
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minItems: 1
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maxItems: 3
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items:
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- description: NAND CTLRDY interrupt
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- description: FLASH_DMA_DONE if flash DMA is available
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- description: FLASH_EDU_DONE if EDU is available
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interrupt-names:
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minItems: 1
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maxItems: 3
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items:
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- const: nand_ctlrdy
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- const: flash_dma_done
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then:
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properties:
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reg-names:
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minItems: 2
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maxItems: 2
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items:
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- const: nand
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- const: nand-int-base
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then:
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properties:
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reg-names:
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minItems: 3
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maxItems: 3
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items:
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- const: nand
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- const: nand-int-base
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then:
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properties:
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reg-names:
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minItems: 3
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maxItems: 3
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items:
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- const: nand
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- const: iproc-idm

‎Documentation/devicetree/bindings/net/dsa/nxp,sja1105.yaml

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reg:
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oneOf:
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- enum:
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- 0
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- 1
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- 0
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- 1
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required:
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- compatible

‎Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml

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@@ -77,6 +77,34 @@ properties:
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Type-C spec states minimum CC pin debounce of 100 ms and maximum
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of 200 ms. However, some solutions might need more than 200 ms.
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refclk-dig:
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type: object
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description: |
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WIZ node should have subnode for refclk_dig to select the reference
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clock source for the reference clock used in the PHY and PMA digital
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logic.
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properties:
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clocks:
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minItems: 2
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maxItems: 4
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description: Phandle to two (Torrent) or four (Sierra) clock nodes representing
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the inputs to refclk_dig
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"#clock-cells":
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const: 0
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assigned-clocks:
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maxItems: 1
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assigned-clock-parents:
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maxItems: 1
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required:
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- clocks
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- "#clock-cells"
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- assigned-clocks
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- assigned-clock-parents
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patternProperties:
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"^pll[0|1]-refclk$":
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type: object
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- clocks
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- "#clock-cells"
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"^refclk-dig$":
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type: object
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description: |
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WIZ node should have subnode for refclk_dig to select the reference
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clock source for the reference clock used in the PHY and PMA digital
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logic.
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properties:
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clocks:
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minItems: 2
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maxItems: 4
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description: Phandle to two (Torrent) or four (Sierra) clock nodes representing
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the inputs to refclk_dig
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"#clock-cells":
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const: 0
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assigned-clocks:
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maxItems: 1
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assigned-clock-parents:
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maxItems: 1
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required:
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- clocks
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- "#clock-cells"
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- assigned-clocks
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- assigned-clock-parents
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"^serdes@[0-9a-f]+$":
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type: object
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description: |

‎Documentation/devicetree/bindings/regulator/mps,mpq7920.yaml

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@@ -36,12 +36,12 @@ properties:
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switching frequency must be one of following corresponding value
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1.1MHz, 1.65MHz, 2.2MHz, 2.75MHz
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patternProperties:
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"^ldo[1-4]$":
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ldortc:
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type: object
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$ref: regulator.yaml#
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"^ldortc$":
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patternProperties:
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"^ldo[1-4]$":
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type: object
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$ref: regulator.yaml#
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‎Documentation/devicetree/bindings/regulator/nxp,pf8x00-regulator.yaml

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@@ -83,7 +83,8 @@ properties:
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unevaluatedProperties: false
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"^vsnvs$":
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properties:
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vsnvs:
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type: object
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$ref: regulator.yaml#
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description:

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