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mbrost05danvet
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drm/i915/guc: Drop guc->interrupts.enabled
Drop the variable guc->interrupts.enabled as this variable is just leading to bugs creeping into the code. e.g. A full GPU reset disables the GuC interrupts but forgot to clear guc->interrupts.enabled, guc->interrupts.enabled being true suppresses interrupts from getting re-enabled and now we are broken. It is harmless to enable interrupt while already enabled so let's just delete this variable to avoid bugs like this going forward. Signed-off-by: Matthew Brost <[email protected]> Reviewed-by: John Harrison <[email protected]> Signed-off-by: Daniel Vetter <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
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2 files changed

+9
-19
lines changed

2 files changed

+9
-19
lines changed

drivers/gpu/drm/i915/gt/uc/intel_guc.c

Lines changed: 9 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -96,12 +96,9 @@ static void gen9_enable_guc_interrupts(struct intel_guc *guc)
9696
assert_rpm_wakelock_held(&gt->i915->runtime_pm);
9797

9898
spin_lock_irq(&gt->irq_lock);
99-
if (!guc->interrupts.enabled) {
100-
WARN_ON_ONCE(intel_uncore_read(gt->uncore, GEN8_GT_IIR(2)) &
101-
gt->pm_guc_events);
102-
guc->interrupts.enabled = true;
103-
gen6_gt_pm_enable_irq(gt, gt->pm_guc_events);
104-
}
99+
WARN_ON_ONCE(intel_uncore_read(gt->uncore, GEN8_GT_IIR(2)) &
100+
gt->pm_guc_events);
101+
gen6_gt_pm_enable_irq(gt, gt->pm_guc_events);
105102
spin_unlock_irq(&gt->irq_lock);
106103
}
107104

@@ -112,7 +109,6 @@ static void gen9_disable_guc_interrupts(struct intel_guc *guc)
112109
assert_rpm_wakelock_held(&gt->i915->runtime_pm);
113110

114111
spin_lock_irq(&gt->irq_lock);
115-
guc->interrupts.enabled = false;
116112

117113
gen6_gt_pm_disable_irq(gt, gt->pm_guc_events);
118114

@@ -134,18 +130,14 @@ static void gen11_reset_guc_interrupts(struct intel_guc *guc)
134130
static void gen11_enable_guc_interrupts(struct intel_guc *guc)
135131
{
136132
struct intel_gt *gt = guc_to_gt(guc);
133+
u32 events = REG_FIELD_PREP(ENGINE1_MASK, GUC_INTR_GUC2HOST);
137134

138135
spin_lock_irq(&gt->irq_lock);
139-
if (!guc->interrupts.enabled) {
140-
u32 events = REG_FIELD_PREP(ENGINE1_MASK, GUC_INTR_GUC2HOST);
141-
142-
WARN_ON_ONCE(gen11_gt_reset_one_iir(gt, 0, GEN11_GUC));
143-
intel_uncore_write(gt->uncore,
144-
GEN11_GUC_SG_INTR_ENABLE, events);
145-
intel_uncore_write(gt->uncore,
146-
GEN11_GUC_SG_INTR_MASK, ~events);
147-
guc->interrupts.enabled = true;
148-
}
136+
WARN_ON_ONCE(gen11_gt_reset_one_iir(gt, 0, GEN11_GUC));
137+
intel_uncore_write(gt->uncore,
138+
GEN11_GUC_SG_INTR_ENABLE, events);
139+
intel_uncore_write(gt->uncore,
140+
GEN11_GUC_SG_INTR_MASK, ~events);
149141
spin_unlock_irq(&gt->irq_lock);
150142
}
151143

@@ -154,7 +146,6 @@ static void gen11_disable_guc_interrupts(struct intel_guc *guc)
154146
struct intel_gt *gt = guc_to_gt(guc);
155147

156148
spin_lock_irq(&gt->irq_lock);
157-
guc->interrupts.enabled = false;
158149

159150
intel_uncore_write(gt->uncore, GEN11_GUC_SG_INTR_MASK, ~0);
160151
intel_uncore_write(gt->uncore, GEN11_GUC_SG_INTR_ENABLE, 0);

drivers/gpu/drm/i915/gt/uc/intel_guc.h

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -33,7 +33,6 @@ struct intel_guc {
3333
unsigned int msg_enabled_mask;
3434

3535
struct {
36-
bool enabled;
3736
void (*reset)(struct intel_guc *guc);
3837
void (*enable)(struct intel_guc *guc);
3938
void (*disable)(struct intel_guc *guc);

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