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drm/i915/dg2: Add forcewake table
The DG2 forcewake table is very similar to the one used by XeHP SDV (and both platforms are even presented as a single table in the bspec). For the most part DG2 starts using a few additional ranges that were 'reserved' on XeHP SDV and stops using some others. However there is a single range (0xd800-0xd87f) that needs to be handled differently between the two platforms (it needs GT wake on XeHP SDV, but render wake on DG2) so unless we want to wake both domains (which could waste power) or define new types of forcewake domains for this special case we need to have separate tables for the two platforms. Let's define the ranges for both platforms with a parameterized macro so that we don't actually need to duplicate everything in the code. It should be fine for DG2 to re-use the Xe_HP shadow register list so we can continue to use the 'xehpsdv' MMIO write functions and don't need to spin up a separate DG2 instance. Bspec: 66534 Cc: Daniele Ceraolo Spurio <[email protected]> Signed-off-by: Matt Roper <[email protected]> Reviewed-by: José Roberto de Souza <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
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‎drivers/gpu/drm/i915/intel_uncore.c

Lines changed: 168 additions & 137 deletions
Original file line numberDiff line numberDiff line change
@@ -1317,143 +1317,170 @@ static const struct intel_forcewake_range __gen12_fw_ranges[] = {
13171317
0x1d3f00 - 0x1d3fff: VD2 */
13181318
};
13191319

1320-
/* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
1321-
static const struct intel_forcewake_range __xehp_fw_ranges[] = {
1322-
GEN_FW_RANGE(0x0, 0x1fff, 0), /*
1323-
0x0 - 0xaff: reserved
1324-
0xb00 - 0x1fff: always on */
1325-
GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER),
1326-
GEN_FW_RANGE(0x2700, 0x4aff, FORCEWAKE_GT),
1327-
GEN_FW_RANGE(0x4b00, 0x51ff, 0), /*
1328-
0x4b00 - 0x4fff: reserved
1329-
0x5000 - 0x51ff: always on */
1330-
GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER),
1331-
GEN_FW_RANGE(0x8000, 0x813f, FORCEWAKE_GT),
1332-
GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER),
1333-
GEN_FW_RANGE(0x8160, 0x81ff, 0), /*
1334-
0x8160 - 0x817f: reserved
1335-
0x8180 - 0x81ff: always on */
1336-
GEN_FW_RANGE(0x8200, 0x82ff, FORCEWAKE_GT),
1337-
GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER),
1338-
GEN_FW_RANGE(0x8500, 0x94cf, FORCEWAKE_GT), /*
1339-
0x8500 - 0x87ff: gt
1340-
0x8800 - 0x8fff: reserved
1341-
0x9000 - 0x947f: gt
1342-
0x9480 - 0x94cf: reserved */
1343-
GEN_FW_RANGE(0x94d0, 0x955f, FORCEWAKE_RENDER),
1344-
GEN_FW_RANGE(0x9560, 0x97ff, 0), /*
1345-
0x9560 - 0x95ff: always on
1346-
0x9600 - 0x97ff: reserved */
1347-
GEN_FW_RANGE(0x9800, 0xcfff, FORCEWAKE_GT), /*
1348-
0x9800 - 0xb4ff: gt
1349-
0xb500 - 0xbfff: reserved
1350-
0xc000 - 0xcfff: gt */
1351-
GEN_FW_RANGE(0xd000, 0xd7ff, 0),
1352-
GEN_FW_RANGE(0xd800, 0xdbff, FORCEWAKE_GT),
1353-
GEN_FW_RANGE(0xdc00, 0xdcff, FORCEWAKE_RENDER),
1354-
GEN_FW_RANGE(0xdd00, 0xde7f, FORCEWAKE_GT), /*
1355-
0xdd00 - 0xddff: gt
1356-
0xde00 - 0xde7f: reserved */
1357-
GEN_FW_RANGE(0xde80, 0xe8ff, FORCEWAKE_RENDER), /*
1358-
0xde80 - 0xdfff: render
1359-
0xe000 - 0xe0ff: reserved
1360-
0xe100 - 0xe8ff: render */
1361-
GEN_FW_RANGE(0xe900, 0xffff, FORCEWAKE_GT), /*
1362-
0xe900 - 0xe9ff: gt
1363-
0xea00 - 0xefff: reserved
1364-
0xf000 - 0xffff: gt */
1365-
GEN_FW_RANGE(0x10000, 0x13fff, 0), /*
1366-
0x10000 - 0x11fff: reserved
1367-
0x12000 - 0x127ff: always on
1368-
0x12800 - 0x13fff: reserved */
1369-
GEN_FW_RANGE(0x14000, 0x141ff, FORCEWAKE_MEDIA_VDBOX0),
1370-
GEN_FW_RANGE(0x14200, 0x143ff, FORCEWAKE_MEDIA_VDBOX2),
1371-
GEN_FW_RANGE(0x14400, 0x145ff, FORCEWAKE_MEDIA_VDBOX4),
1372-
GEN_FW_RANGE(0x14600, 0x147ff, FORCEWAKE_MEDIA_VDBOX6),
1373-
GEN_FW_RANGE(0x14800, 0x1ffff, FORCEWAKE_RENDER), /*
1374-
0x14800 - 0x14fff: render
1375-
0x15000 - 0x16dff: reserved
1376-
0x16e00 - 0x1ffff: render */
1377-
GEN_FW_RANGE(0x20000, 0x21fff, FORCEWAKE_MEDIA_VDBOX0), /*
1378-
0x20000 - 0x20fff: VD0
1379-
0x21000 - 0x21fff: reserved */
1380-
GEN_FW_RANGE(0x22000, 0x23fff, FORCEWAKE_GT),
1381-
GEN_FW_RANGE(0x24000, 0x2417f, 0), /*
1382-
0x24000 - 0x2407f: always on
1383-
0x24080 - 0x2417f: reserved */
1384-
GEN_FW_RANGE(0x24180, 0x249ff, FORCEWAKE_GT), /*
1385-
0x24180 - 0x241ff: gt
1386-
0x24200 - 0x249ff: reserved */
1387-
GEN_FW_RANGE(0x24a00, 0x251ff, FORCEWAKE_RENDER), /*
1388-
0x24a00 - 0x24a7f: render
1389-
0x24a80 - 0x251ff: reserved */
1390-
GEN_FW_RANGE(0x25200, 0x25fff, FORCEWAKE_GT), /*
1391-
0x25200 - 0x252ff: gt
1392-
0x25300 - 0x25fff: reserved */
1393-
GEN_FW_RANGE(0x26000, 0x2ffff, FORCEWAKE_RENDER), /*
1394-
0x26000 - 0x27fff: render
1395-
0x28000 - 0x29fff: reserved
1396-
0x2a000 - 0x2ffff: undocumented */
1397-
GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_GT),
1398-
GEN_FW_RANGE(0x40000, 0x1bffff, 0),
1399-
GEN_FW_RANGE(0x1c0000, 0x1c3fff, FORCEWAKE_MEDIA_VDBOX0), /*
1400-
0x1c0000 - 0x1c2bff: VD0
1401-
0x1c2c00 - 0x1c2cff: reserved
1402-
0x1c2d00 - 0x1c2dff: VD0
1403-
0x1c2e00 - 0x1c3eff: reserved
1404-
0x1c3f00 - 0x1c3fff: VD0 */
1405-
GEN_FW_RANGE(0x1c4000, 0x1c7fff, FORCEWAKE_MEDIA_VDBOX1), /*
1406-
0x1c4000 - 0x1c6bff: VD1
1407-
0x1c6c00 - 0x1c6cff: reserved
1408-
0x1c6d00 - 0x1c6dff: VD1
1409-
0x1c6e00 - 0x1c7fff: reserved */
1410-
GEN_FW_RANGE(0x1c8000, 0x1cbfff, FORCEWAKE_MEDIA_VEBOX0), /*
1411-
0x1c8000 - 0x1ca0ff: VE0
1412-
0x1ca100 - 0x1cbfff: reserved */
1413-
GEN_FW_RANGE(0x1cc000, 0x1ccfff, FORCEWAKE_MEDIA_VDBOX0),
1414-
GEN_FW_RANGE(0x1cd000, 0x1cdfff, FORCEWAKE_MEDIA_VDBOX2),
1415-
GEN_FW_RANGE(0x1ce000, 0x1cefff, FORCEWAKE_MEDIA_VDBOX4),
1416-
GEN_FW_RANGE(0x1cf000, 0x1cffff, FORCEWAKE_MEDIA_VDBOX6),
1417-
GEN_FW_RANGE(0x1d0000, 0x1d3fff, FORCEWAKE_MEDIA_VDBOX2), /*
1418-
0x1d0000 - 0x1d2bff: VD2
1419-
0x1d2c00 - 0x1d2cff: reserved
1420-
0x1d2d00 - 0x1d2dff: VD2
1421-
0x1d2e00 - 0x1d3eff: reserved
1422-
0x1d3f00 - 0x1d3fff: VD2 */
1423-
GEN_FW_RANGE(0x1d4000, 0x1d7fff, FORCEWAKE_MEDIA_VDBOX3), /*
1424-
0x1d4000 - 0x1d6bff: VD3
1425-
0x1d6c00 - 0x1d6cff: reserved
1426-
0x1d6d00 - 0x1d6dff: VD3
1427-
0x1d6e00 - 0x1d7fff: reserved */
1428-
GEN_FW_RANGE(0x1d8000, 0x1dffff, FORCEWAKE_MEDIA_VEBOX1), /*
1429-
0x1d8000 - 0x1da0ff: VE1
1430-
0x1da100 - 0x1dffff: reserved */
1431-
GEN_FW_RANGE(0x1e0000, 0x1e3fff, FORCEWAKE_MEDIA_VDBOX4), /*
1432-
0x1e0000 - 0x1e2bff: VD4
1433-
0x1e2c00 - 0x1e2cff: reserved
1434-
0x1e2d00 - 0x1e2dff: VD4
1435-
0x1e2e00 - 0x1e3eff: reserved
1436-
0x1e3f00 - 0x1e3fff: VD4 */
1437-
GEN_FW_RANGE(0x1e4000, 0x1e7fff, FORCEWAKE_MEDIA_VDBOX5), /*
1438-
0x1e4000 - 0x1e6bff: VD5
1439-
0x1e6c00 - 0x1e6cff: reserved
1440-
0x1e6d00 - 0x1e6dff: VD5
1441-
0x1e6e00 - 0x1e7fff: reserved */
1442-
GEN_FW_RANGE(0x1e8000, 0x1effff, FORCEWAKE_MEDIA_VEBOX2), /*
1443-
0x1e8000 - 0x1ea0ff: VE2
1444-
0x1ea100 - 0x1effff: reserved */
1445-
GEN_FW_RANGE(0x1f0000, 0x1f3fff, FORCEWAKE_MEDIA_VDBOX6), /*
1446-
0x1f0000 - 0x1f2bff: VD6
1447-
0x1f2c00 - 0x1f2cff: reserved
1448-
0x1f2d00 - 0x1f2dff: VD6
1449-
0x1f2e00 - 0x1f3eff: reserved
1450-
0x1f3f00 - 0x1f3fff: VD6 */
1451-
GEN_FW_RANGE(0x1f4000, 0x1f7fff, FORCEWAKE_MEDIA_VDBOX7), /*
1452-
0x1f4000 - 0x1f6bff: VD7
1453-
0x1f6c00 - 0x1f6cff: reserved
1454-
0x1f6d00 - 0x1f6dff: VD7
1455-
0x1f6e00 - 0x1f7fff: reserved */
1320+
/*
1321+
* Graphics IP version 12.55 brings a slight change to the 0xd800 range,
1322+
* switching it from the GT domain to the render domain.
1323+
*
1324+
* *Must* be sorted by offset ranges! See intel_fw_table_check().
1325+
*/
1326+
#define XEHP_FWRANGES(FW_RANGE_D800) \
1327+
GEN_FW_RANGE(0x0, 0x1fff, 0), /* \
1328+
0x0 - 0xaff: reserved \
1329+
0xb00 - 0x1fff: always on */ \
1330+
GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER), \
1331+
GEN_FW_RANGE(0x2700, 0x4aff, FORCEWAKE_GT), \
1332+
GEN_FW_RANGE(0x4b00, 0x51ff, 0), /* \
1333+
0x4b00 - 0x4fff: reserved \
1334+
0x5000 - 0x51ff: always on */ \
1335+
GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER), \
1336+
GEN_FW_RANGE(0x8000, 0x813f, FORCEWAKE_GT), \
1337+
GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER), \
1338+
GEN_FW_RANGE(0x8160, 0x81ff, 0), /* \
1339+
0x8160 - 0x817f: reserved \
1340+
0x8180 - 0x81ff: always on */ \
1341+
GEN_FW_RANGE(0x8200, 0x82ff, FORCEWAKE_GT), \
1342+
GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER), \
1343+
GEN_FW_RANGE(0x8500, 0x8cff, FORCEWAKE_GT), /* \
1344+
0x8500 - 0x87ff: gt \
1345+
0x8800 - 0x8c7f: reserved \
1346+
0x8c80 - 0x8cff: gt (DG2 only) */ \
1347+
GEN_FW_RANGE(0x8d00, 0x8fff, FORCEWAKE_RENDER), /* \
1348+
0x8d00 - 0x8dff: render (DG2 only) \
1349+
0x8e00 - 0x8fff: reserved */ \
1350+
GEN_FW_RANGE(0x9000, 0x94cf, FORCEWAKE_GT), /* \
1351+
0x9000 - 0x947f: gt \
1352+
0x9480 - 0x94cf: reserved */ \
1353+
GEN_FW_RANGE(0x94d0, 0x955f, FORCEWAKE_RENDER), \
1354+
GEN_FW_RANGE(0x9560, 0x967f, 0), /* \
1355+
0x9560 - 0x95ff: always on \
1356+
0x9600 - 0x967f: reserved */ \
1357+
GEN_FW_RANGE(0x9680, 0x97ff, FORCEWAKE_RENDER), /* \
1358+
0x9680 - 0x96ff: render (DG2 only) \
1359+
0x9700 - 0x97ff: reserved */ \
1360+
GEN_FW_RANGE(0x9800, 0xcfff, FORCEWAKE_GT), /* \
1361+
0x9800 - 0xb4ff: gt \
1362+
0xb500 - 0xbfff: reserved \
1363+
0xc000 - 0xcfff: gt */ \
1364+
GEN_FW_RANGE(0xd000, 0xd7ff, 0), \
1365+
GEN_FW_RANGE(0xd800, 0xd87f, FW_RANGE_D800), \
1366+
GEN_FW_RANGE(0xd880, 0xdbff, FORCEWAKE_GT), \
1367+
GEN_FW_RANGE(0xdc00, 0xdcff, FORCEWAKE_RENDER), \
1368+
GEN_FW_RANGE(0xdd00, 0xde7f, FORCEWAKE_GT), /* \
1369+
0xdd00 - 0xddff: gt \
1370+
0xde00 - 0xde7f: reserved */ \
1371+
GEN_FW_RANGE(0xde80, 0xe8ff, FORCEWAKE_RENDER), /* \
1372+
0xde80 - 0xdfff: render \
1373+
0xe000 - 0xe0ff: reserved \
1374+
0xe100 - 0xe8ff: render */ \
1375+
GEN_FW_RANGE(0xe900, 0xffff, FORCEWAKE_GT), /* \
1376+
0xe900 - 0xe9ff: gt \
1377+
0xea00 - 0xefff: reserved \
1378+
0xf000 - 0xffff: gt */ \
1379+
GEN_FW_RANGE(0x10000, 0x12fff, 0), /* \
1380+
0x10000 - 0x11fff: reserved \
1381+
0x12000 - 0x127ff: always on \
1382+
0x12800 - 0x12fff: reserved */ \
1383+
GEN_FW_RANGE(0x13000, 0x131ff, FORCEWAKE_MEDIA_VDBOX0), /* DG2 only */ \
1384+
GEN_FW_RANGE(0x13200, 0x13fff, FORCEWAKE_MEDIA_VDBOX2), /* \
1385+
0x13200 - 0x133ff: VD2 (DG2 only) \
1386+
0x13400 - 0x13fff: reserved */ \
1387+
GEN_FW_RANGE(0x14000, 0x141ff, FORCEWAKE_MEDIA_VDBOX0), /* XEHPSDV only */ \
1388+
GEN_FW_RANGE(0x14200, 0x143ff, FORCEWAKE_MEDIA_VDBOX2), /* XEHPSDV only */ \
1389+
GEN_FW_RANGE(0x14400, 0x145ff, FORCEWAKE_MEDIA_VDBOX4), /* XEHPSDV only */ \
1390+
GEN_FW_RANGE(0x14600, 0x147ff, FORCEWAKE_MEDIA_VDBOX6), /* XEHPSDV only */ \
1391+
GEN_FW_RANGE(0x14800, 0x14fff, FORCEWAKE_RENDER), \
1392+
GEN_FW_RANGE(0x15000, 0x16dff, FORCEWAKE_GT), /* \
1393+
0x15000 - 0x15fff: gt (DG2 only) \
1394+
0x16000 - 0x16dff: reserved */ \
1395+
GEN_FW_RANGE(0x16e00, 0x1ffff, FORCEWAKE_RENDER), \
1396+
GEN_FW_RANGE(0x20000, 0x21fff, FORCEWAKE_MEDIA_VDBOX0), /* \
1397+
0x20000 - 0x20fff: VD0 (XEHPSDV only) \
1398+
0x21000 - 0x21fff: reserved */ \
1399+
GEN_FW_RANGE(0x22000, 0x23fff, FORCEWAKE_GT), \
1400+
GEN_FW_RANGE(0x24000, 0x2417f, 0), /* \
1401+
0x24000 - 0x2407f: always on \
1402+
0x24080 - 0x2417f: reserved */ \
1403+
GEN_FW_RANGE(0x24180, 0x249ff, FORCEWAKE_GT), /* \
1404+
0x24180 - 0x241ff: gt \
1405+
0x24200 - 0x249ff: reserved */ \
1406+
GEN_FW_RANGE(0x24a00, 0x251ff, FORCEWAKE_RENDER), /* \
1407+
0x24a00 - 0x24a7f: render \
1408+
0x24a80 - 0x251ff: reserved */ \
1409+
GEN_FW_RANGE(0x25200, 0x25fff, FORCEWAKE_GT), /* \
1410+
0x25200 - 0x252ff: gt \
1411+
0x25300 - 0x25fff: reserved */ \
1412+
GEN_FW_RANGE(0x26000, 0x2ffff, FORCEWAKE_RENDER), /* \
1413+
0x26000 - 0x27fff: render \
1414+
0x28000 - 0x29fff: reserved \
1415+
0x2a000 - 0x2ffff: undocumented */ \
1416+
GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_GT), \
1417+
GEN_FW_RANGE(0x40000, 0x1bffff, 0), \
1418+
GEN_FW_RANGE(0x1c0000, 0x1c3fff, FORCEWAKE_MEDIA_VDBOX0), /* \
1419+
0x1c0000 - 0x1c2bff: VD0 \
1420+
0x1c2c00 - 0x1c2cff: reserved \
1421+
0x1c2d00 - 0x1c2dff: VD0 \
1422+
0x1c2e00 - 0x1c3eff: VD0 (DG2 only) \
1423+
0x1c3f00 - 0x1c3fff: VD0 */ \
1424+
GEN_FW_RANGE(0x1c4000, 0x1c7fff, FORCEWAKE_MEDIA_VDBOX1), /* \
1425+
0x1c4000 - 0x1c6bff: VD1 \
1426+
0x1c6c00 - 0x1c6cff: reserved \
1427+
0x1c6d00 - 0x1c6dff: VD1 \
1428+
0x1c6e00 - 0x1c7fff: reserved */ \
1429+
GEN_FW_RANGE(0x1c8000, 0x1cbfff, FORCEWAKE_MEDIA_VEBOX0), /* \
1430+
0x1c8000 - 0x1ca0ff: VE0 \
1431+
0x1ca100 - 0x1cbfff: reserved */ \
1432+
GEN_FW_RANGE(0x1cc000, 0x1ccfff, FORCEWAKE_MEDIA_VDBOX0), \
1433+
GEN_FW_RANGE(0x1cd000, 0x1cdfff, FORCEWAKE_MEDIA_VDBOX2), \
1434+
GEN_FW_RANGE(0x1ce000, 0x1cefff, FORCEWAKE_MEDIA_VDBOX4), \
1435+
GEN_FW_RANGE(0x1cf000, 0x1cffff, FORCEWAKE_MEDIA_VDBOX6), \
1436+
GEN_FW_RANGE(0x1d0000, 0x1d3fff, FORCEWAKE_MEDIA_VDBOX2), /* \
1437+
0x1d0000 - 0x1d2bff: VD2 \
1438+
0x1d2c00 - 0x1d2cff: reserved \
1439+
0x1d2d00 - 0x1d2dff: VD2 \
1440+
0x1d2e00 - 0x1d3dff: VD2 (DG2 only) \
1441+
0x1d3e00 - 0x1d3eff: reserved \
1442+
0x1d3f00 - 0x1d3fff: VD2 */ \
1443+
GEN_FW_RANGE(0x1d4000, 0x1d7fff, FORCEWAKE_MEDIA_VDBOX3), /* \
1444+
0x1d4000 - 0x1d6bff: VD3 \
1445+
0x1d6c00 - 0x1d6cff: reserved \
1446+
0x1d6d00 - 0x1d6dff: VD3 \
1447+
0x1d6e00 - 0x1d7fff: reserved */ \
1448+
GEN_FW_RANGE(0x1d8000, 0x1dffff, FORCEWAKE_MEDIA_VEBOX1), /* \
1449+
0x1d8000 - 0x1da0ff: VE1 \
1450+
0x1da100 - 0x1dffff: reserved */ \
1451+
GEN_FW_RANGE(0x1e0000, 0x1e3fff, FORCEWAKE_MEDIA_VDBOX4), /* \
1452+
0x1e0000 - 0x1e2bff: VD4 \
1453+
0x1e2c00 - 0x1e2cff: reserved \
1454+
0x1e2d00 - 0x1e2dff: VD4 \
1455+
0x1e2e00 - 0x1e3eff: reserved \
1456+
0x1e3f00 - 0x1e3fff: VD4 */ \
1457+
GEN_FW_RANGE(0x1e4000, 0x1e7fff, FORCEWAKE_MEDIA_VDBOX5), /* \
1458+
0x1e4000 - 0x1e6bff: VD5 \
1459+
0x1e6c00 - 0x1e6cff: reserved \
1460+
0x1e6d00 - 0x1e6dff: VD5 \
1461+
0x1e6e00 - 0x1e7fff: reserved */ \
1462+
GEN_FW_RANGE(0x1e8000, 0x1effff, FORCEWAKE_MEDIA_VEBOX2), /* \
1463+
0x1e8000 - 0x1ea0ff: VE2 \
1464+
0x1ea100 - 0x1effff: reserved */ \
1465+
GEN_FW_RANGE(0x1f0000, 0x1f3fff, FORCEWAKE_MEDIA_VDBOX6), /* \
1466+
0x1f0000 - 0x1f2bff: VD6 \
1467+
0x1f2c00 - 0x1f2cff: reserved \
1468+
0x1f2d00 - 0x1f2dff: VD6 \
1469+
0x1f2e00 - 0x1f3eff: reserved \
1470+
0x1f3f00 - 0x1f3fff: VD6 */ \
1471+
GEN_FW_RANGE(0x1f4000, 0x1f7fff, FORCEWAKE_MEDIA_VDBOX7), /* \
1472+
0x1f4000 - 0x1f6bff: VD7 \
1473+
0x1f6c00 - 0x1f6cff: reserved \
1474+
0x1f6d00 - 0x1f6dff: VD7 \
1475+
0x1f6e00 - 0x1f7fff: reserved */ \
14561476
GEN_FW_RANGE(0x1f8000, 0x1fa0ff, FORCEWAKE_MEDIA_VEBOX3),
1477+
1478+
static const struct intel_forcewake_range __xehp_fw_ranges[] = {
1479+
XEHP_FWRANGES(FORCEWAKE_GT)
1480+
};
1481+
1482+
static const struct intel_forcewake_range __dg2_fw_ranges[] = {
1483+
XEHP_FWRANGES(FORCEWAKE_RENDER)
14571484
};
14581485

14591486
static void
@@ -2084,7 +2111,11 @@ static int uncore_forcewake_init(struct intel_uncore *uncore)
20842111
return ret;
20852112
forcewake_early_sanitize(uncore, 0);
20862113

2087-
if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) {
2114+
if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55)) {
2115+
ASSIGN_FW_DOMAINS_TABLE(uncore, __dg2_fw_ranges);
2116+
ASSIGN_WRITE_MMIO_VFUNCS(uncore, xehp_fwtable);
2117+
ASSIGN_READ_MMIO_VFUNCS(uncore, gen11_fwtable);
2118+
} else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) {
20882119
ASSIGN_FW_DOMAINS_TABLE(uncore, __xehp_fw_ranges);
20892120
ASSIGN_WRITE_MMIO_VFUNCS(uncore, xehp_fwtable);
20902121
ASSIGN_READ_MMIO_VFUNCS(uncore, gen11_fwtable);

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