@@ -92,18 +92,22 @@ static int pch_pic_set_type(struct irq_data *d, unsigned int type)
92
92
case IRQ_TYPE_EDGE_RISING :
93
93
pch_pic_bitset (priv , PCH_PIC_EDGE , d -> hwirq );
94
94
pch_pic_bitclr (priv , PCH_PIC_POL , d -> hwirq );
95
+ irq_set_handler_locked (d , handle_edge_irq );
95
96
break ;
96
97
case IRQ_TYPE_EDGE_FALLING :
97
98
pch_pic_bitset (priv , PCH_PIC_EDGE , d -> hwirq );
98
99
pch_pic_bitset (priv , PCH_PIC_POL , d -> hwirq );
100
+ irq_set_handler_locked (d , handle_edge_irq );
99
101
break ;
100
102
case IRQ_TYPE_LEVEL_HIGH :
101
103
pch_pic_bitclr (priv , PCH_PIC_EDGE , d -> hwirq );
102
104
pch_pic_bitclr (priv , PCH_PIC_POL , d -> hwirq );
105
+ irq_set_handler_locked (d , handle_level_irq );
103
106
break ;
104
107
case IRQ_TYPE_LEVEL_LOW :
105
108
pch_pic_bitclr (priv , PCH_PIC_EDGE , d -> hwirq );
106
109
pch_pic_bitset (priv , PCH_PIC_POL , d -> hwirq );
110
+ irq_set_handler_locked (d , handle_level_irq );
107
111
break ;
108
112
default :
109
113
ret = - EINVAL ;
@@ -113,11 +117,24 @@ static int pch_pic_set_type(struct irq_data *d, unsigned int type)
113
117
return ret ;
114
118
}
115
119
120
+ static void pch_pic_ack_irq (struct irq_data * d )
121
+ {
122
+ unsigned int reg ;
123
+ struct pch_pic * priv = irq_data_get_irq_chip_data (d );
124
+
125
+ reg = readl (priv -> base + PCH_PIC_EDGE + PIC_REG_IDX (d -> hwirq ) * 4 );
126
+ if (reg & BIT (PIC_REG_BIT (d -> hwirq ))) {
127
+ writel (BIT (PIC_REG_BIT (d -> hwirq )),
128
+ priv -> base + PCH_PIC_CLR + PIC_REG_IDX (d -> hwirq ) * 4 );
129
+ }
130
+ irq_chip_ack_parent (d );
131
+ }
132
+
116
133
static struct irq_chip pch_pic_irq_chip = {
117
134
.name = "PCH PIC" ,
118
135
.irq_mask = pch_pic_mask_irq ,
119
136
.irq_unmask = pch_pic_unmask_irq ,
120
- .irq_ack = irq_chip_ack_parent ,
137
+ .irq_ack = pch_pic_ack_irq ,
121
138
.irq_set_affinity = irq_chip_set_affinity_parent ,
122
139
.irq_set_type = pch_pic_set_type ,
123
140
};
0 commit comments