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parakalinusw
paraka
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linusw
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pinctrl: ralink: move MT7621 SoC pinmux config into a new 'pinctrl-mt7621.c' file
Move all related code for SoC MT7621 into a new driver located in 'pinctrl-mt7621.c' source file. Signed-off-by: Sergio Paracuellos <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
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‎arch/mips/ralink/mt7621.c

Lines changed: 0 additions & 88 deletions
Original file line numberDiff line numberDiff line change
@@ -18,97 +18,10 @@
1818
#include <asm/mach-ralink/ralink_regs.h>
1919
#include <asm/mach-ralink/mt7621.h>
2020

21-
#include <pinmux.h>
22-
2321
#include "common.h"
2422

25-
#define MT7621_GPIO_MODE_UART1 1
26-
#define MT7621_GPIO_MODE_I2C 2
27-
#define MT7621_GPIO_MODE_UART3_MASK 0x3
28-
#define MT7621_GPIO_MODE_UART3_SHIFT 3
29-
#define MT7621_GPIO_MODE_UART3_GPIO 1
30-
#define MT7621_GPIO_MODE_UART2_MASK 0x3
31-
#define MT7621_GPIO_MODE_UART2_SHIFT 5
32-
#define MT7621_GPIO_MODE_UART2_GPIO 1
33-
#define MT7621_GPIO_MODE_JTAG 7
34-
#define MT7621_GPIO_MODE_WDT_MASK 0x3
35-
#define MT7621_GPIO_MODE_WDT_SHIFT 8
36-
#define MT7621_GPIO_MODE_WDT_GPIO 1
37-
#define MT7621_GPIO_MODE_PCIE_RST 0
38-
#define MT7621_GPIO_MODE_PCIE_REF 2
39-
#define MT7621_GPIO_MODE_PCIE_MASK 0x3
40-
#define MT7621_GPIO_MODE_PCIE_SHIFT 10
41-
#define MT7621_GPIO_MODE_PCIE_GPIO 1
42-
#define MT7621_GPIO_MODE_MDIO_MASK 0x3
43-
#define MT7621_GPIO_MODE_MDIO_SHIFT 12
44-
#define MT7621_GPIO_MODE_MDIO_GPIO 1
45-
#define MT7621_GPIO_MODE_RGMII1 14
46-
#define MT7621_GPIO_MODE_RGMII2 15
47-
#define MT7621_GPIO_MODE_SPI_MASK 0x3
48-
#define MT7621_GPIO_MODE_SPI_SHIFT 16
49-
#define MT7621_GPIO_MODE_SPI_GPIO 1
50-
#define MT7621_GPIO_MODE_SDHCI_MASK 0x3
51-
#define MT7621_GPIO_MODE_SDHCI_SHIFT 18
52-
#define MT7621_GPIO_MODE_SDHCI_GPIO 1
53-
5423
static void *detect_magic __initdata = detect_memory_region;
5524

56-
static struct rt2880_pmx_func uart1_grp[] = { FUNC("uart1", 0, 1, 2) };
57-
static struct rt2880_pmx_func i2c_grp[] = { FUNC("i2c", 0, 3, 2) };
58-
static struct rt2880_pmx_func uart3_grp[] = {
59-
FUNC("uart3", 0, 5, 4),
60-
FUNC("i2s", 2, 5, 4),
61-
FUNC("spdif3", 3, 5, 4),
62-
};
63-
static struct rt2880_pmx_func uart2_grp[] = {
64-
FUNC("uart2", 0, 9, 4),
65-
FUNC("pcm", 2, 9, 4),
66-
FUNC("spdif2", 3, 9, 4),
67-
};
68-
static struct rt2880_pmx_func jtag_grp[] = { FUNC("jtag", 0, 13, 5) };
69-
static struct rt2880_pmx_func wdt_grp[] = {
70-
FUNC("wdt rst", 0, 18, 1),
71-
FUNC("wdt refclk", 2, 18, 1),
72-
};
73-
static struct rt2880_pmx_func pcie_rst_grp[] = {
74-
FUNC("pcie rst", MT7621_GPIO_MODE_PCIE_RST, 19, 1),
75-
FUNC("pcie refclk", MT7621_GPIO_MODE_PCIE_REF, 19, 1)
76-
};
77-
static struct rt2880_pmx_func mdio_grp[] = { FUNC("mdio", 0, 20, 2) };
78-
static struct rt2880_pmx_func rgmii2_grp[] = { FUNC("rgmii2", 0, 22, 12) };
79-
static struct rt2880_pmx_func spi_grp[] = {
80-
FUNC("spi", 0, 34, 7),
81-
FUNC("nand1", 2, 34, 7),
82-
};
83-
static struct rt2880_pmx_func sdhci_grp[] = {
84-
FUNC("sdhci", 0, 41, 8),
85-
FUNC("nand2", 2, 41, 8),
86-
};
87-
static struct rt2880_pmx_func rgmii1_grp[] = { FUNC("rgmii1", 0, 49, 12) };
88-
89-
static struct rt2880_pmx_group mt7621_pinmux_data[] = {
90-
GRP("uart1", uart1_grp, 1, MT7621_GPIO_MODE_UART1),
91-
GRP("i2c", i2c_grp, 1, MT7621_GPIO_MODE_I2C),
92-
GRP_G("uart3", uart3_grp, MT7621_GPIO_MODE_UART3_MASK,
93-
MT7621_GPIO_MODE_UART3_GPIO, MT7621_GPIO_MODE_UART3_SHIFT),
94-
GRP_G("uart2", uart2_grp, MT7621_GPIO_MODE_UART2_MASK,
95-
MT7621_GPIO_MODE_UART2_GPIO, MT7621_GPIO_MODE_UART2_SHIFT),
96-
GRP("jtag", jtag_grp, 1, MT7621_GPIO_MODE_JTAG),
97-
GRP_G("wdt", wdt_grp, MT7621_GPIO_MODE_WDT_MASK,
98-
MT7621_GPIO_MODE_WDT_GPIO, MT7621_GPIO_MODE_WDT_SHIFT),
99-
GRP_G("pcie", pcie_rst_grp, MT7621_GPIO_MODE_PCIE_MASK,
100-
MT7621_GPIO_MODE_PCIE_GPIO, MT7621_GPIO_MODE_PCIE_SHIFT),
101-
GRP_G("mdio", mdio_grp, MT7621_GPIO_MODE_MDIO_MASK,
102-
MT7621_GPIO_MODE_MDIO_GPIO, MT7621_GPIO_MODE_MDIO_SHIFT),
103-
GRP("rgmii2", rgmii2_grp, 1, MT7621_GPIO_MODE_RGMII2),
104-
GRP_G("spi", spi_grp, MT7621_GPIO_MODE_SPI_MASK,
105-
MT7621_GPIO_MODE_SPI_GPIO, MT7621_GPIO_MODE_SPI_SHIFT),
106-
GRP_G("sdhci", sdhci_grp, MT7621_GPIO_MODE_SDHCI_MASK,
107-
MT7621_GPIO_MODE_SDHCI_GPIO, MT7621_GPIO_MODE_SDHCI_SHIFT),
108-
GRP("rgmii1", rgmii1_grp, 1, MT7621_GPIO_MODE_RGMII1),
109-
{ 0 }
110-
};
111-
11225
phys_addr_t mips_cpc_default_phys_base(void)
11326
{
11427
panic("Cannot detect cpc address");
@@ -219,7 +132,6 @@ void __init prom_soc_init(struct ralink_soc_info *soc_info)
219132
(rev & CHIP_REV_ECO_MASK));
220133

221134
soc_info->mem_detect = mt7621_memory_detect;
222-
rt2880_pinmux_data = mt7621_pinmux_data;
223135

224136
soc_dev_init(soc_info, rev);
225137

‎drivers/pinctrl/ralink/Kconfig

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -11,4 +11,9 @@ config PINCTRL_RT2880
1111
select PINMUX
1212
select GENERIC_PINCONF
1313

14+
config PINCTRL_MT7621
15+
bool "mt7621 pinctrl driver for RALINK/Mediatek SOCs"
16+
depends on RALINK && SOC_MT7621
17+
select PINCTRL_RT2880
18+
1419
endmenu

‎drivers/pinctrl/ralink/Makefile

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,2 +1,4 @@
11
# SPDX-License-Identifier: GPL-2.0
22
obj-$(CONFIG_PINCTRL_RT2880) += pinctrl-rt2880.o
3+
4+
obj-$(CONFIG_PINCTRL_MT7621) += pinctrl-mt7621.o

‎drivers/pinctrl/ralink/pinctrl-mt7621.c

Lines changed: 116 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,116 @@
1+
// SPDX-License-Identifier: GPL-2.0-only
2+
3+
#include <linux/module.h>
4+
#include <linux/platform_device.h>
5+
#include <linux/of.h>
6+
#include "pinmux.h"
7+
8+
#define MT7621_GPIO_MODE_UART1 1
9+
#define MT7621_GPIO_MODE_I2C 2
10+
#define MT7621_GPIO_MODE_UART3_MASK 0x3
11+
#define MT7621_GPIO_MODE_UART3_SHIFT 3
12+
#define MT7621_GPIO_MODE_UART3_GPIO 1
13+
#define MT7621_GPIO_MODE_UART2_MASK 0x3
14+
#define MT7621_GPIO_MODE_UART2_SHIFT 5
15+
#define MT7621_GPIO_MODE_UART2_GPIO 1
16+
#define MT7621_GPIO_MODE_JTAG 7
17+
#define MT7621_GPIO_MODE_WDT_MASK 0x3
18+
#define MT7621_GPIO_MODE_WDT_SHIFT 8
19+
#define MT7621_GPIO_MODE_WDT_GPIO 1
20+
#define MT7621_GPIO_MODE_PCIE_RST 0
21+
#define MT7621_GPIO_MODE_PCIE_REF 2
22+
#define MT7621_GPIO_MODE_PCIE_MASK 0x3
23+
#define MT7621_GPIO_MODE_PCIE_SHIFT 10
24+
#define MT7621_GPIO_MODE_PCIE_GPIO 1
25+
#define MT7621_GPIO_MODE_MDIO_MASK 0x3
26+
#define MT7621_GPIO_MODE_MDIO_SHIFT 12
27+
#define MT7621_GPIO_MODE_MDIO_GPIO 1
28+
#define MT7621_GPIO_MODE_RGMII1 14
29+
#define MT7621_GPIO_MODE_RGMII2 15
30+
#define MT7621_GPIO_MODE_SPI_MASK 0x3
31+
#define MT7621_GPIO_MODE_SPI_SHIFT 16
32+
#define MT7621_GPIO_MODE_SPI_GPIO 1
33+
#define MT7621_GPIO_MODE_SDHCI_MASK 0x3
34+
#define MT7621_GPIO_MODE_SDHCI_SHIFT 18
35+
#define MT7621_GPIO_MODE_SDHCI_GPIO 1
36+
37+
static struct rt2880_pmx_func uart1_grp[] = { FUNC("uart1", 0, 1, 2) };
38+
static struct rt2880_pmx_func i2c_grp[] = { FUNC("i2c", 0, 3, 2) };
39+
static struct rt2880_pmx_func uart3_grp[] = {
40+
FUNC("uart3", 0, 5, 4),
41+
FUNC("i2s", 2, 5, 4),
42+
FUNC("spdif3", 3, 5, 4),
43+
};
44+
static struct rt2880_pmx_func uart2_grp[] = {
45+
FUNC("uart2", 0, 9, 4),
46+
FUNC("pcm", 2, 9, 4),
47+
FUNC("spdif2", 3, 9, 4),
48+
};
49+
static struct rt2880_pmx_func jtag_grp[] = { FUNC("jtag", 0, 13, 5) };
50+
static struct rt2880_pmx_func wdt_grp[] = {
51+
FUNC("wdt rst", 0, 18, 1),
52+
FUNC("wdt refclk", 2, 18, 1),
53+
};
54+
static struct rt2880_pmx_func pcie_rst_grp[] = {
55+
FUNC("pcie rst", MT7621_GPIO_MODE_PCIE_RST, 19, 1),
56+
FUNC("pcie refclk", MT7621_GPIO_MODE_PCIE_REF, 19, 1)
57+
};
58+
static struct rt2880_pmx_func mdio_grp[] = { FUNC("mdio", 0, 20, 2) };
59+
static struct rt2880_pmx_func rgmii2_grp[] = { FUNC("rgmii2", 0, 22, 12) };
60+
static struct rt2880_pmx_func spi_grp[] = {
61+
FUNC("spi", 0, 34, 7),
62+
FUNC("nand1", 2, 34, 7),
63+
};
64+
static struct rt2880_pmx_func sdhci_grp[] = {
65+
FUNC("sdhci", 0, 41, 8),
66+
FUNC("nand2", 2, 41, 8),
67+
};
68+
static struct rt2880_pmx_func rgmii1_grp[] = { FUNC("rgmii1", 0, 49, 12) };
69+
70+
static struct rt2880_pmx_group mt7621_pinmux_data[] = {
71+
GRP("uart1", uart1_grp, 1, MT7621_GPIO_MODE_UART1),
72+
GRP("i2c", i2c_grp, 1, MT7621_GPIO_MODE_I2C),
73+
GRP_G("uart3", uart3_grp, MT7621_GPIO_MODE_UART3_MASK,
74+
MT7621_GPIO_MODE_UART3_GPIO, MT7621_GPIO_MODE_UART3_SHIFT),
75+
GRP_G("uart2", uart2_grp, MT7621_GPIO_MODE_UART2_MASK,
76+
MT7621_GPIO_MODE_UART2_GPIO, MT7621_GPIO_MODE_UART2_SHIFT),
77+
GRP("jtag", jtag_grp, 1, MT7621_GPIO_MODE_JTAG),
78+
GRP_G("wdt", wdt_grp, MT7621_GPIO_MODE_WDT_MASK,
79+
MT7621_GPIO_MODE_WDT_GPIO, MT7621_GPIO_MODE_WDT_SHIFT),
80+
GRP_G("pcie", pcie_rst_grp, MT7621_GPIO_MODE_PCIE_MASK,
81+
MT7621_GPIO_MODE_PCIE_GPIO, MT7621_GPIO_MODE_PCIE_SHIFT),
82+
GRP_G("mdio", mdio_grp, MT7621_GPIO_MODE_MDIO_MASK,
83+
MT7621_GPIO_MODE_MDIO_GPIO, MT7621_GPIO_MODE_MDIO_SHIFT),
84+
GRP("rgmii2", rgmii2_grp, 1, MT7621_GPIO_MODE_RGMII2),
85+
GRP_G("spi", spi_grp, MT7621_GPIO_MODE_SPI_MASK,
86+
MT7621_GPIO_MODE_SPI_GPIO, MT7621_GPIO_MODE_SPI_SHIFT),
87+
GRP_G("sdhci", sdhci_grp, MT7621_GPIO_MODE_SDHCI_MASK,
88+
MT7621_GPIO_MODE_SDHCI_GPIO, MT7621_GPIO_MODE_SDHCI_SHIFT),
89+
GRP("rgmii1", rgmii1_grp, 1, MT7621_GPIO_MODE_RGMII1),
90+
{ 0 }
91+
};
92+
93+
static int mt7621_pinmux_probe(struct platform_device *pdev)
94+
{
95+
return rt2880_pinmux_init(pdev, mt7621_pinmux_data);
96+
}
97+
98+
static const struct of_device_id mt7621_pinmux_match[] = {
99+
{ .compatible = "ralink,rt2880-pinmux" },
100+
{}
101+
};
102+
MODULE_DEVICE_TABLE(of, mt7621_pinmux_match);
103+
104+
static struct platform_driver mt7621_pinmux_driver = {
105+
.probe = mt7621_pinmux_probe,
106+
.driver = {
107+
.name = "rt2880-pinmux",
108+
.of_match_table = mt7621_pinmux_match,
109+
},
110+
};
111+
112+
static int __init mt7621_pinmux_init(void)
113+
{
114+
return platform_driver_register(&mt7621_pinmux_driver);
115+
}
116+
core_initcall_sync(mt7621_pinmux_init);

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