@@ -342,7 +342,7 @@ struct clk_fixed_rate {
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unsigned long flags ;
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};
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- #define CLK_FIXED_RATE_PARENT_ACCURACY BIT(0)
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+ #define CLK_FIXED_RATE_PARENT_ACCURACY BIT(0)
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extern const struct clk_ops clk_fixed_rate_ops ;
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struct clk_hw * __clk_hw_register_fixed_rate (struct device * dev ,
@@ -1020,8 +1020,8 @@ struct clk_fractional_divider {
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#define to_clk_fd (_hw ) container_of(_hw, struct clk_fractional_divider, hw)
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- #define CLK_FRAC_DIVIDER_ZERO_BASED BIT(0)
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- #define CLK_FRAC_DIVIDER_BIG_ENDIAN BIT(1)
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+ #define CLK_FRAC_DIVIDER_ZERO_BASED BIT(0)
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+ #define CLK_FRAC_DIVIDER_BIG_ENDIAN BIT(1)
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extern const struct clk_ops clk_fractional_divider_ops ;
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struct clk * clk_register_fractional_divider (struct device * dev ,
@@ -1069,9 +1069,9 @@ struct clk_multiplier {
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#define to_clk_multiplier (_hw ) container_of(_hw, struct clk_multiplier, hw)
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- #define CLK_MULTIPLIER_ZERO_BYPASS BIT(0)
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+ #define CLK_MULTIPLIER_ZERO_BYPASS BIT(0)
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#define CLK_MULTIPLIER_ROUND_CLOSEST BIT(1)
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- #define CLK_MULTIPLIER_BIG_ENDIAN BIT(2)
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+ #define CLK_MULTIPLIER_BIG_ENDIAN BIT(2)
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extern const struct clk_ops clk_multiplier_ops ;
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