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torvaldstorvalds
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Merge tag 'drm-fixes-2021-06-11' of git://anongit.freedesktop.org/drm/drm
Pull drm fixes from Dave Airlie: "Another week of fixes, nothing too crazy, but a few all over the place. Two locking fixes in the core/ttm area, a couple of small driver fixes (radeon, sun4i, mcde, vc4). Then msm and amdgpu have a set of fixes each, mostly for smaller things, though the msm has a DSI fix for a black screen. I haven't seen any intel fixes this week so they may have a few that may or may not wait for next week. drm: - auth locking fix ttm: - locking fix amdgpu: - Use kvzmalloc in amdgu_bo_create - Use drm_dbg_kms for reporting failure to get a GEM FB - Fix some register offsets for Sienna Cichlid - Fix fall-through warning radeon: - memcpy_to/from_io fixes msm: - NULL ptr deref fix - CP_PROTECT reg programming fix - incorrect register shift fix - DSI blank screen fix sun4i: - hdmi output probing fix mcde: - DSI pipeline calc fix vc4: - out of bounds fix" * tag 'drm-fixes-2021-06-11' of git://anongit.freedesktop.org/drm/drm: drm/msm/dsi: Stash away calculated vco frequency on recalc drm: Lock pointer access in drm_master_release() drm/mcde: Fix off by 10^3 in calculation drm/msm/a6xx: avoid shadow NULL reference in failure path drm/msm/a6xx: fix incorrectly set uavflagprd_inv field for A650 drm/msm/a6xx: update/fix CP_PROTECT initialization radeon: use memcpy_to/fromio for UVD fw upload drm/amd/pm: Fix fall-through warning for Clang drm/amdgpu: Fix incorrect register offsets for Sienna Cichlid drm/amdgpu: Use drm_dbg_kms for reporting failure to get a GEM FB drm/amdgpu: switch kzalloc to kvzalloc in amdgpu_bo_create drm/msm: Init mm_list before accessing it for use_vram path drm: Fix use-after-free read in drm_getunique() drm/vc4: fix vc4_atomic_commit_tail() logic drm/ttm: fix deref of bo->ttm without holding the lock v2 drm/sun4i: dw-hdmi: Make HDMI PHY into a platform device
2 parents 929d931 + 7de5c0d commit f21b807

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19 files changed

+232
-79
lines changed

19 files changed

+232
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lines changed

‎drivers/gpu/drm/amd/amdgpu/amdgpu_display.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1057,7 +1057,7 @@ int amdgpu_display_gem_fb_init(struct drm_device *dev,
10571057

10581058
return 0;
10591059
err:
1060-
drm_err(dev, "Failed to init gem fb: %d\n", ret);
1060+
drm_dbg_kms(dev, "Failed to init gem fb: %d\n", ret);
10611061
rfb->base.obj[0] = NULL;
10621062
return ret;
10631063
}
@@ -1094,7 +1094,7 @@ int amdgpu_display_gem_fb_verify_and_init(
10941094

10951095
return 0;
10961096
err:
1097-
drm_err(dev, "Failed to verify and init gem fb: %d\n", ret);
1097+
drm_dbg_kms(dev, "Failed to verify and init gem fb: %d\n", ret);
10981098
rfb->base.obj[0] = NULL;
10991099
return ret;
11001100
}

‎drivers/gpu/drm/amd/amdgpu/amdgpu_object.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -100,7 +100,7 @@ static void amdgpu_bo_destroy(struct ttm_buffer_object *tbo)
100100
kfree(ubo->metadata);
101101
}
102102

103-
kfree(bo);
103+
kvfree(bo);
104104
}
105105

106106
/**
@@ -552,7 +552,7 @@ static int amdgpu_bo_do_create(struct amdgpu_device *adev,
552552
BUG_ON(bp->bo_ptr_size < sizeof(struct amdgpu_bo));
553553

554554
*bo_ptr = NULL;
555-
bo = kzalloc(bp->bo_ptr_size, GFP_KERNEL);
555+
bo = kvzalloc(bp->bo_ptr_size, GFP_KERNEL);
556556
if (bo == NULL)
557557
return -ENOMEM;
558558
drm_gem_private_object_init(adev_to_drm(adev), &bo->tbo.base, size);

‎drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

Lines changed: 21 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -173,6 +173,9 @@
173173
#define mmGC_THROTTLE_CTRL_Sienna_Cichlid 0x2030
174174
#define mmGC_THROTTLE_CTRL_Sienna_Cichlid_BASE_IDX 0
175175

176+
#define mmRLC_SPARE_INT_0_Sienna_Cichlid 0x4ca5
177+
#define mmRLC_SPARE_INT_0_Sienna_Cichlid_BASE_IDX 1
178+
176179
#define GFX_RLCG_GC_WRITE_OLD (0x8 << 28)
177180
#define GFX_RLCG_GC_WRITE (0x0 << 28)
178181
#define GFX_RLCG_GC_READ (0x1 << 28)
@@ -1480,8 +1483,15 @@ static u32 gfx_v10_rlcg_rw(struct amdgpu_device *adev, u32 offset, u32 v, uint32
14801483
(adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG0_BASE_IDX] + mmSCRATCH_REG2) * 4;
14811484
scratch_reg3 = adev->rmmio +
14821485
(adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG3) * 4;
1483-
spare_int = adev->rmmio +
1484-
(adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_BASE_IDX] + mmRLC_SPARE_INT) * 4;
1486+
1487+
if (adev->asic_type >= CHIP_SIENNA_CICHLID) {
1488+
spare_int = adev->rmmio +
1489+
(adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_0_Sienna_Cichlid_BASE_IDX]
1490+
+ mmRLC_SPARE_INT_0_Sienna_Cichlid) * 4;
1491+
} else {
1492+
spare_int = adev->rmmio +
1493+
(adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_BASE_IDX] + mmRLC_SPARE_INT) * 4;
1494+
}
14851495

14861496
grbm_cntl = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_CNTL_BASE_IDX] + mmGRBM_GFX_CNTL;
14871497
grbm_idx = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_INDEX_BASE_IDX] + mmGRBM_GFX_INDEX;
@@ -7349,9 +7359,15 @@ static int gfx_v10_0_hw_fini(void *handle)
73497359
if (amdgpu_sriov_vf(adev)) {
73507360
gfx_v10_0_cp_gfx_enable(adev, false);
73517361
/* Program KIQ position of RLC_CP_SCHEDULERS during destroy */
7352-
tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
7353-
tmp &= 0xffffff00;
7354-
WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
7362+
if (adev->asic_type >= CHIP_SIENNA_CICHLID) {
7363+
tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid);
7364+
tmp &= 0xffffff00;
7365+
WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp);
7366+
} else {
7367+
tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
7368+
tmp &= 0xffffff00;
7369+
WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
7370+
}
73557371

73567372
return 0;
73577373
}

‎drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -810,6 +810,7 @@ static int smu10_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
810810
break;
811811
case AMD_DPM_FORCED_LEVEL_MANUAL:
812812
data->fine_grain_enabled = 1;
813+
break;
813814
case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
814815
default:
815816
break;

‎drivers/gpu/drm/drm_auth.c

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -314,9 +314,10 @@ int drm_master_open(struct drm_file *file_priv)
314314
void drm_master_release(struct drm_file *file_priv)
315315
{
316316
struct drm_device *dev = file_priv->minor->dev;
317-
struct drm_master *master = file_priv->master;
317+
struct drm_master *master;
318318

319319
mutex_lock(&dev->master_mutex);
320+
master = file_priv->master;
320321
if (file_priv->magic)
321322
idr_remove(&file_priv->master->magic_map, file_priv->magic);
322323

‎drivers/gpu/drm/drm_ioctl.c

Lines changed: 5 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -118,17 +118,18 @@ int drm_getunique(struct drm_device *dev, void *data,
118118
struct drm_file *file_priv)
119119
{
120120
struct drm_unique *u = data;
121-
struct drm_master *master = file_priv->master;
121+
struct drm_master *master;
122122

123-
mutex_lock(&master->dev->master_mutex);
123+
mutex_lock(&dev->master_mutex);
124+
master = file_priv->master;
124125
if (u->unique_len >= master->unique_len) {
125126
if (copy_to_user(u->unique, master->unique, master->unique_len)) {
126-
mutex_unlock(&master->dev->master_mutex);
127+
mutex_unlock(&dev->master_mutex);
127128
return -EFAULT;
128129
}
129130
}
130131
u->unique_len = master->unique_len;
131-
mutex_unlock(&master->dev->master_mutex);
132+
mutex_unlock(&dev->master_mutex);
132133

133134
return 0;
134135
}

‎drivers/gpu/drm/mcde/mcde_dsi.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -577,7 +577,7 @@ static void mcde_dsi_setup_video_mode(struct mcde_dsi *d,
577577
* porches and sync.
578578
*/
579579
/* (ps/s) / (pixels/s) = ps/pixels */
580-
pclk = DIV_ROUND_UP_ULL(1000000000000, mode->clock);
580+
pclk = DIV_ROUND_UP_ULL(1000000000000, (mode->clock * 1000));
581581
dev_dbg(d->dev, "picoseconds between two pixels: %llu\n",
582582
pclk);
583583

‎drivers/gpu/drm/msm/adreno/a6xx_gpu.c

Lines changed: 114 additions & 41 deletions
Original file line numberDiff line numberDiff line change
@@ -157,7 +157,7 @@ static void a6xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit)
157157
* GPU registers so we need to add 0x1a800 to the register value on A630
158158
* to get the right value from PM4.
159159
*/
160-
get_stats_counter(ring, REG_A6XX_GMU_ALWAYS_ON_COUNTER_L + 0x1a800,
160+
get_stats_counter(ring, REG_A6XX_CP_ALWAYS_ON_COUNTER_LO,
161161
rbmemptr_stats(ring, index, alwayson_start));
162162

163163
/* Invalidate CCU depth and color */
@@ -187,7 +187,7 @@ static void a6xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit)
187187

188188
get_stats_counter(ring, REG_A6XX_RBBM_PERFCTR_CP_0_LO,
189189
rbmemptr_stats(ring, index, cpcycles_end));
190-
get_stats_counter(ring, REG_A6XX_GMU_ALWAYS_ON_COUNTER_L + 0x1a800,
190+
get_stats_counter(ring, REG_A6XX_CP_ALWAYS_ON_COUNTER_LO,
191191
rbmemptr_stats(ring, index, alwayson_end));
192192

193193
/* Write the fence to the scratch register */
@@ -206,8 +206,8 @@ static void a6xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit)
206206
OUT_RING(ring, submit->seqno);
207207

208208
trace_msm_gpu_submit_flush(submit,
209-
gmu_read64(&a6xx_gpu->gmu, REG_A6XX_GMU_ALWAYS_ON_COUNTER_L,
210-
REG_A6XX_GMU_ALWAYS_ON_COUNTER_H));
209+
gpu_read64(gpu, REG_A6XX_CP_ALWAYS_ON_COUNTER_LO,
210+
REG_A6XX_CP_ALWAYS_ON_COUNTER_HI));
211211

212212
a6xx_flush(gpu, ring);
213213
}
@@ -462,6 +462,113 @@ static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state)
462462
gpu_write(gpu, REG_A6XX_RBBM_CLOCK_CNTL, state ? clock_cntl_on : 0);
463463
}
464464

465+
/* For a615, a616, a618, A619, a630, a640 and a680 */
466+
static const u32 a6xx_protect[] = {
467+
A6XX_PROTECT_RDONLY(0x00000, 0x04ff),
468+
A6XX_PROTECT_RDONLY(0x00501, 0x0005),
469+
A6XX_PROTECT_RDONLY(0x0050b, 0x02f4),
470+
A6XX_PROTECT_NORDWR(0x0050e, 0x0000),
471+
A6XX_PROTECT_NORDWR(0x00510, 0x0000),
472+
A6XX_PROTECT_NORDWR(0x00534, 0x0000),
473+
A6XX_PROTECT_NORDWR(0x00800, 0x0082),
474+
A6XX_PROTECT_NORDWR(0x008a0, 0x0008),
475+
A6XX_PROTECT_NORDWR(0x008ab, 0x0024),
476+
A6XX_PROTECT_RDONLY(0x008de, 0x00ae),
477+
A6XX_PROTECT_NORDWR(0x00900, 0x004d),
478+
A6XX_PROTECT_NORDWR(0x0098d, 0x0272),
479+
A6XX_PROTECT_NORDWR(0x00e00, 0x0001),
480+
A6XX_PROTECT_NORDWR(0x00e03, 0x000c),
481+
A6XX_PROTECT_NORDWR(0x03c00, 0x00c3),
482+
A6XX_PROTECT_RDONLY(0x03cc4, 0x1fff),
483+
A6XX_PROTECT_NORDWR(0x08630, 0x01cf),
484+
A6XX_PROTECT_NORDWR(0x08e00, 0x0000),
485+
A6XX_PROTECT_NORDWR(0x08e08, 0x0000),
486+
A6XX_PROTECT_NORDWR(0x08e50, 0x001f),
487+
A6XX_PROTECT_NORDWR(0x09624, 0x01db),
488+
A6XX_PROTECT_NORDWR(0x09e70, 0x0001),
489+
A6XX_PROTECT_NORDWR(0x09e78, 0x0187),
490+
A6XX_PROTECT_NORDWR(0x0a630, 0x01cf),
491+
A6XX_PROTECT_NORDWR(0x0ae02, 0x0000),
492+
A6XX_PROTECT_NORDWR(0x0ae50, 0x032f),
493+
A6XX_PROTECT_NORDWR(0x0b604, 0x0000),
494+
A6XX_PROTECT_NORDWR(0x0be02, 0x0001),
495+
A6XX_PROTECT_NORDWR(0x0be20, 0x17df),
496+
A6XX_PROTECT_NORDWR(0x0f000, 0x0bff),
497+
A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff),
498+
A6XX_PROTECT_NORDWR(0x11c00, 0x0000), /* note: infinite range */
499+
};
500+
501+
/* These are for a620 and a650 */
502+
static const u32 a650_protect[] = {
503+
A6XX_PROTECT_RDONLY(0x00000, 0x04ff),
504+
A6XX_PROTECT_RDONLY(0x00501, 0x0005),
505+
A6XX_PROTECT_RDONLY(0x0050b, 0x02f4),
506+
A6XX_PROTECT_NORDWR(0x0050e, 0x0000),
507+
A6XX_PROTECT_NORDWR(0x00510, 0x0000),
508+
A6XX_PROTECT_NORDWR(0x00534, 0x0000),
509+
A6XX_PROTECT_NORDWR(0x00800, 0x0082),
510+
A6XX_PROTECT_NORDWR(0x008a0, 0x0008),
511+
A6XX_PROTECT_NORDWR(0x008ab, 0x0024),
512+
A6XX_PROTECT_RDONLY(0x008de, 0x00ae),
513+
A6XX_PROTECT_NORDWR(0x00900, 0x004d),
514+
A6XX_PROTECT_NORDWR(0x0098d, 0x0272),
515+
A6XX_PROTECT_NORDWR(0x00e00, 0x0001),
516+
A6XX_PROTECT_NORDWR(0x00e03, 0x000c),
517+
A6XX_PROTECT_NORDWR(0x03c00, 0x00c3),
518+
A6XX_PROTECT_RDONLY(0x03cc4, 0x1fff),
519+
A6XX_PROTECT_NORDWR(0x08630, 0x01cf),
520+
A6XX_PROTECT_NORDWR(0x08e00, 0x0000),
521+
A6XX_PROTECT_NORDWR(0x08e08, 0x0000),
522+
A6XX_PROTECT_NORDWR(0x08e50, 0x001f),
523+
A6XX_PROTECT_NORDWR(0x08e80, 0x027f),
524+
A6XX_PROTECT_NORDWR(0x09624, 0x01db),
525+
A6XX_PROTECT_NORDWR(0x09e60, 0x0011),
526+
A6XX_PROTECT_NORDWR(0x09e78, 0x0187),
527+
A6XX_PROTECT_NORDWR(0x0a630, 0x01cf),
528+
A6XX_PROTECT_NORDWR(0x0ae02, 0x0000),
529+
A6XX_PROTECT_NORDWR(0x0ae50, 0x032f),
530+
A6XX_PROTECT_NORDWR(0x0b604, 0x0000),
531+
A6XX_PROTECT_NORDWR(0x0b608, 0x0007),
532+
A6XX_PROTECT_NORDWR(0x0be02, 0x0001),
533+
A6XX_PROTECT_NORDWR(0x0be20, 0x17df),
534+
A6XX_PROTECT_NORDWR(0x0f000, 0x0bff),
535+
A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff),
536+
A6XX_PROTECT_NORDWR(0x18400, 0x1fff),
537+
A6XX_PROTECT_NORDWR(0x1a800, 0x1fff),
538+
A6XX_PROTECT_NORDWR(0x1f400, 0x0443),
539+
A6XX_PROTECT_RDONLY(0x1f844, 0x007b),
540+
A6XX_PROTECT_NORDWR(0x1f887, 0x001b),
541+
A6XX_PROTECT_NORDWR(0x1f8c0, 0x0000), /* note: infinite range */
542+
};
543+
544+
static void a6xx_set_cp_protect(struct msm_gpu *gpu)
545+
{
546+
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
547+
const u32 *regs = a6xx_protect;
548+
unsigned i, count = ARRAY_SIZE(a6xx_protect), count_max = 32;
549+
550+
BUILD_BUG_ON(ARRAY_SIZE(a6xx_protect) > 32);
551+
BUILD_BUG_ON(ARRAY_SIZE(a650_protect) > 48);
552+
553+
if (adreno_is_a650(adreno_gpu)) {
554+
regs = a650_protect;
555+
count = ARRAY_SIZE(a650_protect);
556+
count_max = 48;
557+
}
558+
559+
/*
560+
* Enable access protection to privileged registers, fault on an access
561+
* protect violation and select the last span to protect from the start
562+
* address all the way to the end of the register address space
563+
*/
564+
gpu_write(gpu, REG_A6XX_CP_PROTECT_CNTL, BIT(0) | BIT(1) | BIT(3));
565+
566+
for (i = 0; i < count - 1; i++)
567+
gpu_write(gpu, REG_A6XX_CP_PROTECT(i), regs[i]);
568+
/* last CP_PROTECT to have "infinite" length on the last entry */
569+
gpu_write(gpu, REG_A6XX_CP_PROTECT(count_max - 1), regs[i]);
570+
}
571+
465572
static void a6xx_set_ubwc_config(struct msm_gpu *gpu)
466573
{
467574
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
@@ -489,7 +596,7 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu)
489596
rgb565_predicator << 11 | amsbc << 4 | lower_bit << 1);
490597
gpu_write(gpu, REG_A6XX_TPL1_NC_MODE_CNTL, lower_bit << 1);
491598
gpu_write(gpu, REG_A6XX_SP_NC_MODE_CNTL,
492-
uavflagprd_inv >> 4 | lower_bit << 1);
599+
uavflagprd_inv << 4 | lower_bit << 1);
493600
gpu_write(gpu, REG_A6XX_UCHE_MODE_CNTL, lower_bit << 21);
494601
}
495602

@@ -776,41 +883,7 @@ static int a6xx_hw_init(struct msm_gpu *gpu)
776883
}
777884

778885
/* Protect registers from the CP */
779-
gpu_write(gpu, REG_A6XX_CP_PROTECT_CNTL, 0x00000003);
780-
781-
gpu_write(gpu, REG_A6XX_CP_PROTECT(0),
782-
A6XX_PROTECT_RDONLY(0x600, 0x51));
783-
gpu_write(gpu, REG_A6XX_CP_PROTECT(1), A6XX_PROTECT_RW(0xae50, 0x2));
784-
gpu_write(gpu, REG_A6XX_CP_PROTECT(2), A6XX_PROTECT_RW(0x9624, 0x13));
785-
gpu_write(gpu, REG_A6XX_CP_PROTECT(3), A6XX_PROTECT_RW(0x8630, 0x8));
786-
gpu_write(gpu, REG_A6XX_CP_PROTECT(4), A6XX_PROTECT_RW(0x9e70, 0x1));
787-
gpu_write(gpu, REG_A6XX_CP_PROTECT(5), A6XX_PROTECT_RW(0x9e78, 0x187));
788-
gpu_write(gpu, REG_A6XX_CP_PROTECT(6), A6XX_PROTECT_RW(0xf000, 0x810));
789-
gpu_write(gpu, REG_A6XX_CP_PROTECT(7),
790-
A6XX_PROTECT_RDONLY(0xfc00, 0x3));
791-
gpu_write(gpu, REG_A6XX_CP_PROTECT(8), A6XX_PROTECT_RW(0x50e, 0x0));
792-
gpu_write(gpu, REG_A6XX_CP_PROTECT(9), A6XX_PROTECT_RDONLY(0x50f, 0x0));
793-
gpu_write(gpu, REG_A6XX_CP_PROTECT(10), A6XX_PROTECT_RW(0x510, 0x0));
794-
gpu_write(gpu, REG_A6XX_CP_PROTECT(11),
795-
A6XX_PROTECT_RDONLY(0x0, 0x4f9));
796-
gpu_write(gpu, REG_A6XX_CP_PROTECT(12),
797-
A6XX_PROTECT_RDONLY(0x501, 0xa));
798-
gpu_write(gpu, REG_A6XX_CP_PROTECT(13),
799-
A6XX_PROTECT_RDONLY(0x511, 0x44));
800-
gpu_write(gpu, REG_A6XX_CP_PROTECT(14), A6XX_PROTECT_RW(0xe00, 0xe));
801-
gpu_write(gpu, REG_A6XX_CP_PROTECT(15), A6XX_PROTECT_RW(0x8e00, 0x0));
802-
gpu_write(gpu, REG_A6XX_CP_PROTECT(16), A6XX_PROTECT_RW(0x8e50, 0xf));
803-
gpu_write(gpu, REG_A6XX_CP_PROTECT(17), A6XX_PROTECT_RW(0xbe02, 0x0));
804-
gpu_write(gpu, REG_A6XX_CP_PROTECT(18),
805-
A6XX_PROTECT_RW(0xbe20, 0x11f3));
806-
gpu_write(gpu, REG_A6XX_CP_PROTECT(19), A6XX_PROTECT_RW(0x800, 0x82));
807-
gpu_write(gpu, REG_A6XX_CP_PROTECT(20), A6XX_PROTECT_RW(0x8a0, 0x8));
808-
gpu_write(gpu, REG_A6XX_CP_PROTECT(21), A6XX_PROTECT_RW(0x8ab, 0x19));
809-
gpu_write(gpu, REG_A6XX_CP_PROTECT(22), A6XX_PROTECT_RW(0x900, 0x4d));
810-
gpu_write(gpu, REG_A6XX_CP_PROTECT(23), A6XX_PROTECT_RW(0x98d, 0x76));
811-
gpu_write(gpu, REG_A6XX_CP_PROTECT(24),
812-
A6XX_PROTECT_RDONLY(0x980, 0x4));
813-
gpu_write(gpu, REG_A6XX_CP_PROTECT(25), A6XX_PROTECT_RW(0xa630, 0x0));
886+
a6xx_set_cp_protect(gpu);
814887

815888
/* Enable expanded apriv for targets that support it */
816889
if (gpu->hw_apriv) {
@@ -1211,7 +1284,7 @@ static int a6xx_pm_suspend(struct msm_gpu *gpu)
12111284
if (ret)
12121285
return ret;
12131286

1214-
if (adreno_gpu->base.hw_apriv || a6xx_gpu->has_whereami)
1287+
if (a6xx_gpu->shadow_bo)
12151288
for (i = 0; i < gpu->nr_rings; i++)
12161289
a6xx_gpu->shadow[i] = 0;
12171290

‎drivers/gpu/drm/msm/adreno/a6xx_gpu.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -44,7 +44,7 @@ struct a6xx_gpu {
4444
* REG_CP_PROTECT_REG(n) - this will block both reads and writes for _len
4545
* registers starting at _reg.
4646
*/
47-
#define A6XX_PROTECT_RW(_reg, _len) \
47+
#define A6XX_PROTECT_NORDWR(_reg, _len) \
4848
((1 << 31) | \
4949
(((_len) & 0x3FFF) << 18) | ((_reg) & 0x3FFFF))
5050

‎drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -432,6 +432,7 @@ static unsigned long dsi_pll_10nm_vco_recalc_rate(struct clk_hw *hw,
432432
pll_freq += div_u64(tmp64, multiplier);
433433

434434
vco_rate = pll_freq;
435+
pll_10nm->vco_current_rate = vco_rate;
435436

436437
DBG("DSI PLL%d returning vco rate = %lu, dec = %x, frac = %x",
437438
pll_10nm->phy->id, (unsigned long)vco_rate, dec, frac);

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