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Merge tag 'perf-tools-fixes-for-v5.13-2021-05-28' of git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux
Pull perf tools fixes from Arnaldo Carvalho de Melo: - Fix error checking of BPF prog attachment in 'perf stat'. - Fix getting maximum number of fds in the vendor events JSON parser. - Move debug initialization earlier, fixing a segfault in some cases. - Fix eventcode of power10 JSON events. * tag 'perf-tools-fixes-for-v5.13-2021-05-28' of git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux: perf vendor events powerpc: Fix eventcode of power10 JSON events perf stat: Fix error check for bpf_program__attach perf debug: Move debug initialization earlier perf jevents: Fix getting maximum number of fds
2 parents 7c0ec89 + 8fc4e4a commit f289d99

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lines changed

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‎tools/perf/perf.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -443,6 +443,8 @@ int main(int argc, const char **argv)
443443
const char *cmd;
444444
char sbuf[STRERR_BUFSIZE];
445445

446+
perf_debug_setup();
447+
446448
/* libsubcmd init */
447449
exec_cmd_init("perf", PREFIX, PERF_EXEC_PATH, EXEC_PATH_ENVIRONMENT);
448450
pager_init(PERF_PAGER_ENVIRONMENT);
@@ -531,8 +533,6 @@ int main(int argc, const char **argv)
531533
*/
532534
pthread__block_sigwinch();
533535

534-
perf_debug_setup();
535-
536536
while (1) {
537537
static int done_help;
538538

‎tools/perf/pmu-events/arch/powerpc/power10/cache.json

Lines changed: 20 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -1,46 +1,56 @@
11
[
22
{
3-
"EventCode": "1003C",
3+
"EventCode": "0x1003C",
44
"EventName": "PM_EXEC_STALL_DMISS_L2L3",
55
"BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for a load miss to resolve from either the local L2 or local L3."
66
},
77
{
8-
"EventCode": "34056",
8+
"EventCode": "0x1E054",
9+
"EventName": "PM_EXEC_STALL_DMISS_L21_L31",
10+
"BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for a load miss to resolve from another core's L2 or L3 on the same chip."
11+
},
12+
{
13+
"EventCode": "0x34054",
14+
"EventName": "PM_EXEC_STALL_DMISS_L2L3_NOCONFLICT",
15+
"BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for a load miss to resolve from the local L2 or local L3, without a dispatch conflict."
16+
},
17+
{
18+
"EventCode": "0x34056",
919
"EventName": "PM_EXEC_STALL_LOAD_FINISH",
10-
"BriefDescription": "Cycles in which the oldest instruction in the pipeline was finishing a load after its data was reloaded from a data source beyond the local L1; cycles in which the LSU was processing an L1-hit; cycles in which the NTF instruction merged with another load in the LMQ."
20+
"BriefDescription": "Cycles in which the oldest instruction in the pipeline was finishing a load after its data was reloaded from a data source beyond the local L1; cycles in which the LSU was processing an L1-hit; cycles in which the NTF instruction merged with another load in the LMQ; cycles in which the NTF instruction is waiting for a data reload for a load miss, but the data comes back with a non-NTF instruction."
1121
},
1222
{
13-
"EventCode": "3006C",
23+
"EventCode": "0x3006C",
1424
"EventName": "PM_RUN_CYC_SMT2_MODE",
1525
"BriefDescription": "Cycles when this thread's run latch is set and the core is in SMT2 mode."
1626
},
1727
{
18-
"EventCode": "300F4",
28+
"EventCode": "0x300F4",
1929
"EventName": "PM_RUN_INST_CMPL_CONC",
2030
"BriefDescription": "PowerPC instructions completed by this thread when all threads in the core had the run-latch set."
2131
},
2232
{
23-
"EventCode": "4C016",
33+
"EventCode": "0x4C016",
2434
"EventName": "PM_EXEC_STALL_DMISS_L2L3_CONFLICT",
2535
"BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for a load miss to resolve from the local L2 or local L3, with a dispatch conflict."
2636
},
2737
{
28-
"EventCode": "4D014",
38+
"EventCode": "0x4D014",
2939
"EventName": "PM_EXEC_STALL_LOAD",
3040
"BriefDescription": "Cycles in which the oldest instruction in the pipeline was a load instruction executing in the Load Store Unit."
3141
},
3242
{
33-
"EventCode": "4D016",
43+
"EventCode": "0x4D016",
3444
"EventName": "PM_EXEC_STALL_PTESYNC",
3545
"BriefDescription": "Cycles in which the oldest instruction in the pipeline was a PTESYNC instruction executing in the Load Store Unit."
3646
},
3747
{
38-
"EventCode": "401EA",
48+
"EventCode": "0x401EA",
3949
"EventName": "PM_THRESH_EXC_128",
4050
"BriefDescription": "Threshold counter exceeded a value of 128."
4151
},
4252
{
43-
"EventCode": "400F6",
53+
"EventCode": "0x400F6",
4454
"EventName": "PM_BR_MPRED_CMPL",
4555
"BriefDescription": "A mispredicted branch completed. Includes direction and target."
4656
}

‎tools/perf/pmu-events/arch/powerpc/power10/floating_point.json

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
[
22
{
3-
"EventCode": "4016E",
3+
"EventCode": "0x4016E",
44
"EventName": "PM_THRESH_NOT_MET",
55
"BriefDescription": "Threshold counter did not meet threshold."
66
}

‎tools/perf/pmu-events/arch/powerpc/power10/frontend.json

Lines changed: 77 additions & 47 deletions
Original file line numberDiff line numberDiff line change
@@ -1,216 +1,246 @@
11
[
22
{
3-
"EventCode": "10004",
3+
"EventCode": "0x10004",
44
"EventName": "PM_EXEC_STALL_TRANSLATION",
55
"BriefDescription": "Cycles in which the oldest instruction in the pipeline suffered a TLB miss or ERAT miss and waited for it to resolve."
66
},
77
{
8-
"EventCode": "10010",
8+
"EventCode": "0x10006",
9+
"EventName": "PM_DISP_STALL_HELD_OTHER_CYC",
10+
"BriefDescription": "Cycles in which the NTC instruction is held at dispatch for any other reason."
11+
},
12+
{
13+
"EventCode": "0x10010",
914
"EventName": "PM_PMC4_OVERFLOW",
1015
"BriefDescription": "The event selected for PMC4 caused the event counter to overflow."
1116
},
1217
{
13-
"EventCode": "10020",
18+
"EventCode": "0x10020",
1419
"EventName": "PM_PMC4_REWIND",
1520
"BriefDescription": "The speculative event selected for PMC4 rewinds and the counter for PMC4 is not charged."
1621
},
1722
{
18-
"EventCode": "10038",
23+
"EventCode": "0x10038",
1924
"EventName": "PM_DISP_STALL_TRANSLATION",
2025
"BriefDescription": "Cycles when dispatch was stalled for this thread because the MMU was handling a translation miss."
2126
},
2227
{
23-
"EventCode": "1003A",
28+
"EventCode": "0x1003A",
2429
"EventName": "PM_DISP_STALL_BR_MPRED_IC_L2",
2530
"BriefDescription": "Cycles when dispatch was stalled while the instruction was fetched from the local L2 after suffering a branch mispredict."
2631
},
2732
{
28-
"EventCode": "1E050",
33+
"EventCode": "0x1D05E",
34+
"EventName": "PM_DISP_STALL_HELD_HALT_CYC",
35+
"BriefDescription": "Cycles in which the NTC instruction is held at dispatch because of power management."
36+
},
37+
{
38+
"EventCode": "0x1E050",
2939
"EventName": "PM_DISP_STALL_HELD_STF_MAPPER_CYC",
3040
"BriefDescription": "Cycles in which the NTC instruction is held at dispatch because the STF mapper/SRB was full. Includes GPR (count, link, tar), VSR, VMR, FPR."
3141
},
3242
{
33-
"EventCode": "1F054",
43+
"EventCode": "0x1F054",
3444
"EventName": "PM_DTLB_HIT",
3545
"BriefDescription": "The PTE required by the instruction was resident in the TLB (data TLB access). When MMCR1[16]=0 this event counts only demand hits. When MMCR1[16]=1 this event includes demand and prefetch. Applies to both HPT and RPT."
3646
},
3747
{
38-
"EventCode": "101E8",
48+
"EventCode": "0x10064",
49+
"EventName": "PM_DISP_STALL_IC_L2",
50+
"BriefDescription": "Cycles when dispatch was stalled while the instruction was fetched from the local L2."
51+
},
52+
{
53+
"EventCode": "0x101E8",
3954
"EventName": "PM_THRESH_EXC_256",
4055
"BriefDescription": "Threshold counter exceeded a count of 256."
4156
},
4257
{
43-
"EventCode": "101EC",
58+
"EventCode": "0x101EC",
4459
"EventName": "PM_THRESH_MET",
4560
"BriefDescription": "Threshold exceeded."
4661
},
4762
{
48-
"EventCode": "100F2",
63+
"EventCode": "0x100F2",
4964
"EventName": "PM_1PLUS_PPC_CMPL",
5065
"BriefDescription": "Cycles in which at least one instruction is completed by this thread."
5166
},
5267
{
53-
"EventCode": "100F6",
68+
"EventCode": "0x100F6",
5469
"EventName": "PM_IERAT_MISS",
5570
"BriefDescription": "IERAT Reloaded to satisfy an IERAT miss. All page sizes are counted by this event."
5671
},
5772
{
58-
"EventCode": "100F8",
73+
"EventCode": "0x100F8",
5974
"EventName": "PM_DISP_STALL_CYC",
6075
"BriefDescription": "Cycles the ICT has no itags assigned to this thread (no instructions were dispatched during these cycles)."
6176
},
6277
{
63-
"EventCode": "20114",
78+
"EventCode": "0x20006",
79+
"EventName": "PM_DISP_STALL_HELD_ISSQ_FULL_CYC",
80+
"BriefDescription": "Cycles in which the NTC instruction is held at dispatch due to Issue queue full. Includes issue queue and branch queue."
81+
},
82+
{
83+
"EventCode": "0x20114",
6484
"EventName": "PM_MRK_L2_RC_DISP",
6585
"BriefDescription": "Marked instruction RC dispatched in L2."
6686
},
6787
{
68-
"EventCode": "2C010",
88+
"EventCode": "0x2C010",
6989
"EventName": "PM_EXEC_STALL_LSU",
7090
"BriefDescription": "Cycles in which the oldest instruction in the pipeline was executing in the Load Store Unit. This does not include simple fixed point instructions."
7191
},
7292
{
73-
"EventCode": "2C016",
93+
"EventCode": "0x2C016",
7494
"EventName": "PM_DISP_STALL_IERAT_ONLY_MISS",
7595
"BriefDescription": "Cycles when dispatch was stalled while waiting to resolve an instruction ERAT miss."
7696
},
7797
{
78-
"EventCode": "2C01E",
98+
"EventCode": "0x2C01E",
7999
"EventName": "PM_DISP_STALL_BR_MPRED_IC_L3",
80100
"BriefDescription": "Cycles when dispatch was stalled while the instruction was fetched from the local L3 after suffering a branch mispredict."
81101
},
82102
{
83-
"EventCode": "2D01A",
103+
"EventCode": "0x2D01A",
84104
"EventName": "PM_DISP_STALL_IC_MISS",
85105
"BriefDescription": "Cycles when dispatch was stalled for this thread due to an Icache Miss."
86106
},
87107
{
88-
"EventCode": "2D01C",
89-
"EventName": "PM_CMPL_STALL_STCX",
90-
"BriefDescription": "Cycles in which the oldest instruction in the pipeline was a stcx waiting for resolution from the nest before completing."
91-
},
92-
{
93-
"EventCode": "2E018",
108+
"EventCode": "0x2E018",
94109
"EventName": "PM_DISP_STALL_FETCH",
95110
"BriefDescription": "Cycles when dispatch was stalled for this thread because Fetch was being held."
96111
},
97112
{
98-
"EventCode": "2E01A",
113+
"EventCode": "0x2E01A",
99114
"EventName": "PM_DISP_STALL_HELD_XVFC_MAPPER_CYC",
100115
"BriefDescription": "Cycles in which the NTC instruction is held at dispatch because the XVFC mapper/SRB was full."
101116
},
102117
{
103-
"EventCode": "2C142",
118+
"EventCode": "0x2C142",
104119
"EventName": "PM_MRK_XFER_FROM_SRC_PMC2",
105120
"BriefDescription": "For a marked data transfer instruction, the processor's L1 data cache was reloaded from the source specified in MMCR3[15:27]. If MMCR1[16|17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloads."
106121
},
107122
{
108-
"EventCode": "24050",
123+
"EventCode": "0x24050",
109124
"EventName": "PM_IOPS_DISP",
110125
"BriefDescription": "Internal Operations dispatched. PM_IOPS_DISP / PM_INST_DISP will show the average number of internal operations per PowerPC instruction."
111126
},
112127
{
113-
"EventCode": "2405E",
128+
"EventCode": "0x2405E",
114129
"EventName": "PM_ISSUE_CANCEL",
115130
"BriefDescription": "An instruction issued and the issue was later cancelled. Only one cancel per PowerPC instruction."
116131
},
117132
{
118-
"EventCode": "200FA",
133+
"EventCode": "0x200FA",
119134
"EventName": "PM_BR_TAKEN_CMPL",
120135
"BriefDescription": "Branch Taken instruction completed."
121136
},
122137
{
123-
"EventCode": "30012",
138+
"EventCode": "0x30004",
139+
"EventName": "PM_DISP_STALL_FLUSH",
140+
"BriefDescription": "Cycles when dispatch was stalled because of a flush that happened to an instruction(s) that was not yet NTC. PM_EXEC_STALL_NTC_FLUSH only includes instructions that were flushed after becoming NTC."
141+
},
142+
{
143+
"EventCode": "0x3000A",
144+
"EventName": "PM_DISP_STALL_ITLB_MISS",
145+
"BriefDescription": "Cycles when dispatch was stalled while waiting to resolve an instruction TLB miss."
146+
},
147+
{
148+
"EventCode": "0x30012",
124149
"EventName": "PM_FLUSH_COMPLETION",
125150
"BriefDescription": "The instruction that was next to complete (oldest in the pipeline) did not complete because it suffered a flush."
126151
},
127152
{
128-
"EventCode": "30014",
153+
"EventCode": "0x30014",
129154
"EventName": "PM_EXEC_STALL_STORE",
130155
"BriefDescription": "Cycles in which the oldest instruction in the pipeline was a store instruction executing in the Load Store Unit."
131156
},
132157
{
133-
"EventCode": "30018",
158+
"EventCode": "0x30018",
134159
"EventName": "PM_DISP_STALL_HELD_SCOREBOARD_CYC",
135160
"BriefDescription": "Cycles in which the NTC instruction is held at dispatch while waiting on the Scoreboard. This event combines VSCR and FPSCR together."
136161
},
137162
{
138-
"EventCode": "30026",
163+
"EventCode": "0x30026",
139164
"EventName": "PM_EXEC_STALL_STORE_MISS",
140165
"BriefDescription": "Cycles in which the oldest instruction in the pipeline was a store whose cache line was not resident in the L1 and was waiting for allocation of the missing line into the L1."
141166
},
142167
{
143-
"EventCode": "3012A",
168+
"EventCode": "0x3012A",
144169
"EventName": "PM_MRK_L2_RC_DONE",
145170
"BriefDescription": "L2 RC machine completed the transaction for the marked instruction."
146171
},
147172
{
148-
"EventCode": "3F046",
173+
"EventCode": "0x3F046",
149174
"EventName": "PM_ITLB_HIT_1G",
150175
"BriefDescription": "Instruction TLB hit (IERAT reload) page size 1G, which implies Radix Page Table translation is in use. When MMCR1[17]=0 this event counts only for demand misses. When MMCR1[17]=1 this event includes demand misses and prefetches."
151176
},
152177
{
153-
"EventCode": "34058",
178+
"EventCode": "0x34058",
154179
"EventName": "PM_DISP_STALL_BR_MPRED_ICMISS",
155180
"BriefDescription": "Cycles when dispatch was stalled after a mispredicted branch resulted in an instruction cache miss."
156181
},
157182
{
158-
"EventCode": "3D05C",
183+
"EventCode": "0x3D05C",
159184
"EventName": "PM_DISP_STALL_HELD_RENAME_CYC",
160185
"BriefDescription": "Cycles in which the NTC instruction is held at dispatch because the mapper/SRB was full. Includes GPR (count, link, tar), VSR, VMR, FPR and XVFC."
161186
},
162187
{
163-
"EventCode": "3E052",
188+
"EventCode": "0x3E052",
164189
"EventName": "PM_DISP_STALL_IC_L3",
165190
"BriefDescription": "Cycles when dispatch was stalled while the instruction was fetched from the local L3."
166191
},
167192
{
168-
"EventCode": "3E054",
193+
"EventCode": "0x3E054",
169194
"EventName": "PM_LD_MISS_L1",
170195
"BriefDescription": "Load Missed L1, counted at execution time (can be greater than loads finished). LMQ merges are not included in this count. i.e. if a load instruction misses on an address that is already allocated on the LMQ, this event will not increment for that load). Note that this count is per slice, so if a load spans multiple slices this event will increment multiple times for a single load."
171196
},
172197
{
173-
"EventCode": "301EA",
198+
"EventCode": "0x301EA",
174199
"EventName": "PM_THRESH_EXC_1024",
175200
"BriefDescription": "Threshold counter exceeded a value of 1024."
176201
},
177202
{
178-
"EventCode": "300FA",
203+
"EventCode": "0x300FA",
179204
"EventName": "PM_INST_FROM_L3MISS",
180205
"BriefDescription": "The processor's instruction cache was reloaded from a source other than the local core's L1, L2, or L3 due to a demand miss."
181206
},
182207
{
183-
"EventCode": "40006",
208+
"EventCode": "0x40006",
184209
"EventName": "PM_ISSUE_KILL",
185210
"BriefDescription": "Cycles in which an instruction or group of instructions were cancelled after being issued. This event increments once per occurrence, regardless of how many instructions are included in the issue group."
186211
},
187212
{
188-
"EventCode": "40116",
213+
"EventCode": "0x40116",
189214
"EventName": "PM_MRK_LARX_FIN",
190215
"BriefDescription": "Marked load and reserve instruction (LARX) finished. LARX and STCX are instructions used to acquire a lock."
191216
},
192217
{
193-
"EventCode": "4C010",
218+
"EventCode": "0x4C010",
194219
"EventName": "PM_DISP_STALL_BR_MPRED_IC_L3MISS",
195220
"BriefDescription": "Cycles when dispatch was stalled while the instruction was fetched from sources beyond the local L3 after suffering a mispredicted branch."
196221
},
197222
{
198-
"EventCode": "4D01E",
223+
"EventCode": "0x4D01E",
199224
"EventName": "PM_DISP_STALL_BR_MPRED",
200225
"BriefDescription": "Cycles when dispatch was stalled for this thread due to a mispredicted branch."
201226
},
202227
{
203-
"EventCode": "4E010",
228+
"EventCode": "0x4E010",
204229
"EventName": "PM_DISP_STALL_IC_L3MISS",
205230
"BriefDescription": "Cycles when dispatch was stalled while the instruction was fetched from any source beyond the local L3."
206231
},
207232
{
208-
"EventCode": "4E01A",
233+
"EventCode": "0x4E01A",
209234
"EventName": "PM_DISP_STALL_HELD_CYC",
210235
"BriefDescription": "Cycles in which the NTC instruction is held at dispatch for any reason."
211236
},
212237
{
213-
"EventCode": "44056",
238+
"EventCode": "0x4003C",
239+
"EventName": "PM_DISP_STALL_HELD_SYNC_CYC",
240+
"BriefDescription": "Cycles in which the NTC instruction is held at dispatch because of a synchronizing instruction that requires the ICT to be empty before dispatch."
241+
},
242+
{
243+
"EventCode": "0x44056",
214244
"EventName": "PM_VECTOR_ST_CMPL",
215245
"BriefDescription": "Vector store instructions completed."
216246
}

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