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Sanjay R Mehtavinodkoul
Sanjay R Mehta
authored and
vinodkoul
committed
dmaengine: ptdma: Initial driver for the AMD PTDMA
Add support for AMD PTDMA controller. It performs high-bandwidth memory to memory and IO copy operation. Device commands are managed via a circular queue of 'descriptors', each of which specifies source and destination addresses for copying a single buffer of data. Signed-off-by: Sanjay R Mehta <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
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‎MAINTAINERS

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@@ -979,6 +979,12 @@ S: Supported
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T: git https://gitlab.freedesktop.org/agd5f/linux.git
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F: drivers/gpu/drm/amd/pm/powerplay/
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+AMD PTDMA DRIVER
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+M: Sanjay R Mehta <[email protected]>
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+L: [email protected]
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+S: Maintained
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+F: drivers/dma/ptdma/
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AMD SEATTLE DEVICE TREE SUPPORT
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M: Brijesh Singh <[email protected]>
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M: Suravee Suthikulpanit <[email protected]>

‎drivers/dma/Kconfig

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@@ -738,6 +738,8 @@ source "drivers/dma/bestcomm/Kconfig"
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source "drivers/dma/mediatek/Kconfig"
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source "drivers/dma/ptdma/Kconfig"
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source "drivers/dma/qcom/Kconfig"
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source "drivers/dma/dw/Kconfig"

‎drivers/dma/Makefile

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@@ -16,6 +16,7 @@ obj-$(CONFIG_DMATEST) += dmatest.o
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obj-$(CONFIG_ALTERA_MSGDMA) += altera-msgdma.o
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obj-$(CONFIG_AMBA_PL08X) += amba-pl08x.o
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obj-$(CONFIG_AMCC_PPC440SPE_ADMA) += ppc4xx/
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obj-$(CONFIG_AMD_PTDMA) += ptdma/
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obj-$(CONFIG_AT_HDMAC) += at_hdmac.o
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obj-$(CONFIG_AT_XDMAC) += at_xdmac.o
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obj-$(CONFIG_AXI_DMAC) += dma-axi-dmac.o

‎drivers/dma/ptdma/Kconfig

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# SPDX-License-Identifier: GPL-2.0-only
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config AMD_PTDMA
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tristate "AMD PassThru DMA Engine"
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depends on X86_64 && PCI
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help
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Enable support for the AMD PTDMA controller. This controller
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provides DMA capabilities to perform high bandwidth memory to
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memory and IO copy operations. It performs DMA transfer through
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queue-based descriptor management. This DMA controller is intended
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to be used with AMD Non-Transparent Bridge devices and not for
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general purpose peripheral DMA.

‎drivers/dma/ptdma/Makefile

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# SPDX-License-Identifier: GPL-2.0-only
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#
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# AMD Passthru DMA driver
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#
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obj-$(CONFIG_AMD_PTDMA) += ptdma.o
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ptdma-objs := ptdma-dev.o
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ptdma-$(CONFIG_PCI) += ptdma-pci.o

‎drivers/dma/ptdma/ptdma-dev.c

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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* AMD Passthru DMA device driver
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* -- Based on the CCP driver
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*
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* Copyright (C) 2016,2021 Advanced Micro Devices, Inc.
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*
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* Author: Sanjay R Mehta <[email protected]>
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* Author: Gary R Hook <[email protected]>
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*/
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#include <linux/bitfield.h>
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#include <linux/dma-mapping.h>
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#include <linux/debugfs.h>
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include "ptdma.h"
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/* Human-readable error strings */
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static char *pt_error_codes[] = {
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"",
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"ERR 01: ILLEGAL_ENGINE",
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"ERR 03: ILLEGAL_FUNCTION_TYPE",
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"ERR 04: ILLEGAL_FUNCTION_MODE",
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"ERR 06: ILLEGAL_FUNCTION_SIZE",
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"ERR 08: ILLEGAL_FUNCTION_RSVD",
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"ERR 09: ILLEGAL_BUFFER_LENGTH",
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"ERR 10: VLSB_FAULT",
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"ERR 11: ILLEGAL_MEM_ADDR",
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"ERR 12: ILLEGAL_MEM_SEL",
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"ERR 13: ILLEGAL_CONTEXT_ID",
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"ERR 15: 0xF Reserved",
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"ERR 18: CMD_TIMEOUT",
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"ERR 19: IDMA0_AXI_SLVERR",
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"ERR 20: IDMA0_AXI_DECERR",
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"ERR 21: 0x15 Reserved",
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"ERR 22: IDMA1_AXI_SLAVE_FAULT",
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"ERR 23: IDMA1_AIXI_DECERR",
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"ERR 24: 0x18 Reserved",
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"ERR 27: 0x1B Reserved",
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"ERR 38: ODMA0_AXI_SLVERR",
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"ERR 39: ODMA0_AXI_DECERR",
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"ERR 40: 0x28 Reserved",
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"ERR 41: ODMA1_AXI_SLVERR",
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"ERR 42: ODMA1_AXI_DECERR",
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"ERR 43: LSB_PARITY_ERR",
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};
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static void pt_log_error(struct pt_device *d, int e)
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{
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dev_err(d->dev, "PTDMA error: %s (0x%x)\n", pt_error_codes[e], e);
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}
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void pt_start_queue(struct pt_cmd_queue *cmd_q)
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{
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/* Turn on the run bit */
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iowrite32(cmd_q->qcontrol | CMD_Q_RUN, cmd_q->reg_control);
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}
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void pt_stop_queue(struct pt_cmd_queue *cmd_q)
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{
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/* Turn off the run bit */
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iowrite32(cmd_q->qcontrol & ~CMD_Q_RUN, cmd_q->reg_control);
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}
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static int pt_core_execute_cmd(struct ptdma_desc *desc, struct pt_cmd_queue *cmd_q)
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{
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bool soc = FIELD_GET(DWORD0_SOC, desc->dw0);
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u8 *q_desc = (u8 *)&cmd_q->qbase[cmd_q->qidx];
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u32 tail;
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if (soc) {
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desc->dw0 |= FIELD_PREP(DWORD0_IOC, desc->dw0);
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desc->dw0 &= ~DWORD0_SOC;
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}
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mutex_lock(&cmd_q->q_mutex);
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/* Copy 32-byte command descriptor to hw queue. */
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memcpy(q_desc, desc, 32);
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cmd_q->qidx = (cmd_q->qidx + 1) % CMD_Q_LEN;
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/* The data used by this command must be flushed to memory */
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wmb();
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/* Write the new tail address back to the queue register */
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tail = lower_32_bits(cmd_q->qdma_tail + cmd_q->qidx * Q_DESC_SIZE);
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iowrite32(tail, cmd_q->reg_control + 0x0004);
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/* Turn the queue back on using our cached control register */
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pt_start_queue(cmd_q);
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mutex_unlock(&cmd_q->q_mutex);
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return 0;
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}
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int pt_core_perform_passthru(struct pt_cmd_queue *cmd_q,
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struct pt_passthru_engine *pt_engine)
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{
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struct ptdma_desc desc;
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cmd_q->cmd_error = 0;
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memset(&desc, 0, sizeof(desc));
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desc.dw0 = CMD_DESC_DW0_VAL;
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desc.length = pt_engine->src_len;
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desc.src_lo = lower_32_bits(pt_engine->src_dma);
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desc.dw3.src_hi = upper_32_bits(pt_engine->src_dma);
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desc.dst_lo = lower_32_bits(pt_engine->dst_dma);
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desc.dw5.dst_hi = upper_32_bits(pt_engine->dst_dma);
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return pt_core_execute_cmd(&desc, cmd_q);
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}
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static inline void pt_core_disable_queue_interrupts(struct pt_device *pt)
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{
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iowrite32(0, pt->cmd_q.reg_control + 0x000C);
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}
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static inline void pt_core_enable_queue_interrupts(struct pt_device *pt)
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{
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iowrite32(SUPPORTED_INTERRUPTS, pt->cmd_q.reg_control + 0x000C);
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}
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static irqreturn_t pt_core_irq_handler(int irq, void *data)
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{
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struct pt_device *pt = data;
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struct pt_cmd_queue *cmd_q = &pt->cmd_q;
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u32 status;
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pt_core_disable_queue_interrupts(pt);
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status = ioread32(cmd_q->reg_control + 0x0010);
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if (status) {
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cmd_q->int_status = status;
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cmd_q->q_status = ioread32(cmd_q->reg_control + 0x0100);
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cmd_q->q_int_status = ioread32(cmd_q->reg_control + 0x0104);
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/* On error, only save the first error value */
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if ((status & INT_ERROR) && !cmd_q->cmd_error)
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cmd_q->cmd_error = CMD_Q_ERROR(cmd_q->q_status);
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/* Acknowledge the interrupt */
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iowrite32(status, cmd_q->reg_control + 0x0010);
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pt_core_enable_queue_interrupts(pt);
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}
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return IRQ_HANDLED;
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}
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int pt_core_init(struct pt_device *pt)
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{
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char dma_pool_name[MAX_DMAPOOL_NAME_LEN];
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struct pt_cmd_queue *cmd_q = &pt->cmd_q;
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u32 dma_addr_lo, dma_addr_hi;
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struct device *dev = pt->dev;
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struct dma_pool *dma_pool;
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int ret;
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/* Allocate a dma pool for the queue */
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snprintf(dma_pool_name, sizeof(dma_pool_name), "%s_q", dev_name(pt->dev));
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dma_pool = dma_pool_create(dma_pool_name, dev,
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PT_DMAPOOL_MAX_SIZE,
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PT_DMAPOOL_ALIGN, 0);
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if (!dma_pool)
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return -ENOMEM;
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/* ptdma core initialisation */
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iowrite32(CMD_CONFIG_VHB_EN, pt->io_regs + CMD_CONFIG_OFFSET);
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iowrite32(CMD_QUEUE_PRIO, pt->io_regs + CMD_QUEUE_PRIO_OFFSET);
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iowrite32(CMD_TIMEOUT_DISABLE, pt->io_regs + CMD_TIMEOUT_OFFSET);
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iowrite32(CMD_CLK_GATE_CONFIG, pt->io_regs + CMD_CLK_GATE_CTL_OFFSET);
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iowrite32(CMD_CONFIG_REQID, pt->io_regs + CMD_REQID_CONFIG_OFFSET);
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cmd_q->pt = pt;
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cmd_q->dma_pool = dma_pool;
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mutex_init(&cmd_q->q_mutex);
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/* Page alignment satisfies our needs for N <= 128 */
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cmd_q->qsize = Q_SIZE(Q_DESC_SIZE);
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cmd_q->qbase = dma_alloc_coherent(dev, cmd_q->qsize,
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&cmd_q->qbase_dma,
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GFP_KERNEL);
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if (!cmd_q->qbase) {
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dev_err(dev, "unable to allocate command queue\n");
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ret = -ENOMEM;
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goto e_dma_alloc;
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}
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cmd_q->qidx = 0;
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/* Preset some register values */
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cmd_q->reg_control = pt->io_regs + CMD_Q_STATUS_INCR;
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/* Turn off the queues and disable interrupts until ready */
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pt_core_disable_queue_interrupts(pt);
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cmd_q->qcontrol = 0; /* Start with nothing */
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iowrite32(cmd_q->qcontrol, cmd_q->reg_control);
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ioread32(cmd_q->reg_control + 0x0104);
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ioread32(cmd_q->reg_control + 0x0100);
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/* Clear the interrupt status */
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iowrite32(SUPPORTED_INTERRUPTS, cmd_q->reg_control + 0x0010);
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/* Request an irq */
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ret = request_irq(pt->pt_irq, pt_core_irq_handler, 0, dev_name(pt->dev), pt);
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if (ret)
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goto e_pool;
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/* Update the device registers with queue information. */
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cmd_q->qcontrol &= ~CMD_Q_SIZE;
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cmd_q->qcontrol |= FIELD_PREP(CMD_Q_SIZE, QUEUE_SIZE_VAL);
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cmd_q->qdma_tail = cmd_q->qbase_dma;
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dma_addr_lo = lower_32_bits(cmd_q->qdma_tail);
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iowrite32((u32)dma_addr_lo, cmd_q->reg_control + 0x0004);
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iowrite32((u32)dma_addr_lo, cmd_q->reg_control + 0x0008);
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dma_addr_hi = upper_32_bits(cmd_q->qdma_tail);
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cmd_q->qcontrol |= (dma_addr_hi << 16);
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iowrite32(cmd_q->qcontrol, cmd_q->reg_control);
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pt_core_enable_queue_interrupts(pt);
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return 0;
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e_dma_alloc:
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dma_free_coherent(dev, cmd_q->qsize, cmd_q->qbase, cmd_q->qbase_dma);
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e_pool:
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dev_err(dev, "unable to allocate an IRQ\n");
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dma_pool_destroy(pt->cmd_q.dma_pool);
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return ret;
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}
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void pt_core_destroy(struct pt_device *pt)
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{
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struct device *dev = pt->dev;
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struct pt_cmd_queue *cmd_q = &pt->cmd_q;
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struct pt_cmd *cmd;
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/* Disable and clear interrupts */
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pt_core_disable_queue_interrupts(pt);
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/* Turn off the run bit */
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pt_stop_queue(cmd_q);
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/* Clear the interrupt status */
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iowrite32(SUPPORTED_INTERRUPTS, cmd_q->reg_control + 0x0010);
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ioread32(cmd_q->reg_control + 0x0104);
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ioread32(cmd_q->reg_control + 0x0100);
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free_irq(pt->pt_irq, pt);
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dma_free_coherent(dev, cmd_q->qsize, cmd_q->qbase,
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cmd_q->qbase_dma);
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/* Flush the cmd queue */
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while (!list_empty(&pt->cmd)) {
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/* Invoke the callback directly with an error code */
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cmd = list_first_entry(&pt->cmd, struct pt_cmd, entry);
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list_del(&cmd->entry);
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cmd->pt_cmd_callback(cmd->data, -ENODEV);
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}
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}

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