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gpu: host1x: debug: Dump DMASTART and DMAEND register
Show the values of the DMASTART and DMAEND registers when dumping status to help with failure analysis. Signed-off-by: Thierry Reding <[email protected]>
1 parent afa770f commit fed0289

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2 files changed

+21
-3
lines changed

2 files changed

+21
-3
lines changed

drivers/gpu/host1x/hw/debug_hw_1x01.c

Lines changed: 6 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -16,10 +16,13 @@ static void host1x_debug_show_channel_cdma(struct host1x *host,
1616
struct output *o)
1717
{
1818
struct host1x_cdma *cdma = &ch->cdma;
19+
dma_addr_t dmastart, dmaend;
1920
u32 dmaput, dmaget, dmactrl;
2021
u32 cbstat, cbread;
2122
u32 val, base, baseval;
2223

24+
dmastart = host1x_ch_readl(ch, HOST1X_CHANNEL_DMASTART);
25+
dmaend = host1x_ch_readl(ch, HOST1X_CHANNEL_DMAEND);
2326
dmaput = host1x_ch_readl(ch, HOST1X_CHANNEL_DMAPUT);
2427
dmaget = host1x_ch_readl(ch, HOST1X_CHANNEL_DMAGET);
2528
dmactrl = host1x_ch_readl(ch, HOST1X_CHANNEL_DMACTRL);
@@ -56,9 +59,10 @@ static void host1x_debug_show_channel_cdma(struct host1x *host,
5659
HOST1X_SYNC_CBSTAT_CBOFFSET_V(cbstat),
5760
cbread);
5861

59-
host1x_debug_output(o, "DMAPUT %08x, DMAGET %08x, DMACTL %08x\n",
62+
host1x_debug_output(o, "DMASTART %pad, DMAEND %pad\n", &dmastart, &dmaend);
63+
host1x_debug_output(o, "DMAPUT %08x DMAGET %08x DMACTL %08x\n",
6064
dmaput, dmaget, dmactrl);
61-
host1x_debug_output(o, "CBREAD %08x, CBSTAT %08x\n", cbread, cbstat);
65+
host1x_debug_output(o, "CBREAD %08x CBSTAT %08x\n", cbread, cbstat);
6266

6367
show_channel_gathers(o, cdma);
6468
host1x_debug_output(o, "\n");

drivers/gpu/host1x/hw/debug_hw_1x06.c

Lines changed: 15 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -16,10 +16,23 @@ static void host1x_debug_show_channel_cdma(struct host1x *host,
1616
struct output *o)
1717
{
1818
struct host1x_cdma *cdma = &ch->cdma;
19+
dma_addr_t dmastart = 0, dmaend = 0;
1920
u32 dmaput, dmaget, dmactrl;
2021
u32 offset, class;
2122
u32 ch_stat;
2223

24+
#if defined(CONFIG_ARCH_DMA_ADDR_T_64BIT) && HOST1X_HW >= 6
25+
dmastart = host1x_ch_readl(ch, HOST1X_CHANNEL_DMASTART_HI);
26+
dmastart <<= 32;
27+
#endif
28+
dmastart |= host1x_ch_readl(ch, HOST1X_CHANNEL_DMASTART);
29+
30+
#if defined(CONFIG_ARCH_DMA_ADDR_T_64BIT) && HOST1X_HW >= 6
31+
dmaend = host1x_ch_readl(ch, HOST1X_CHANNEL_DMAEND_HI);
32+
dmaend <<= 32;
33+
#endif
34+
dmaend |= host1x_ch_readl(ch, HOST1X_CHANNEL_DMAEND);
35+
2336
dmaput = host1x_ch_readl(ch, HOST1X_CHANNEL_DMAPUT);
2437
dmaget = host1x_ch_readl(ch, HOST1X_CHANNEL_DMAGET);
2538
dmactrl = host1x_ch_readl(ch, HOST1X_CHANNEL_DMACTRL);
@@ -41,7 +54,8 @@ static void host1x_debug_show_channel_cdma(struct host1x *host,
4154
host1x_debug_output(o, "active class %02x, offset %04x\n",
4255
class, offset);
4356

44-
host1x_debug_output(o, "DMAPUT %08x, DMAGET %08x, DMACTL %08x\n",
57+
host1x_debug_output(o, "DMASTART %pad, DMAEND %pad\n", &dmastart, &dmaend);
58+
host1x_debug_output(o, "DMAPUT %08x DMAGET %08x DMACTL %08x\n",
4559
dmaput, dmaget, dmactrl);
4660
host1x_debug_output(o, "CHANNELSTAT %02x\n", ch_stat);
4761

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