diff --git a/boards/ambiq/apollo4p_blue_kbr_evb/Kconfig.apollo4p_blue_kbr_evb b/boards/ambiq/apollo4p_blue_kbr_evb/Kconfig.apollo4p_blue_kbr_evb new file mode 100644 index 0000000000000..3ab21fab83365 --- /dev/null +++ b/boards/ambiq/apollo4p_blue_kbr_evb/Kconfig.apollo4p_blue_kbr_evb @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2025 Ambiq Micro Inc. + +config BOARD_APOLLO4P_BLUE_KBR_EVB + select SOC_APOLLO4P_BLUE diff --git a/boards/ambiq/apollo4p_blue_kbr_evb/Kconfig.defconfig b/boards/ambiq/apollo4p_blue_kbr_evb/Kconfig.defconfig new file mode 100644 index 0000000000000..fa81a4363f376 --- /dev/null +++ b/boards/ambiq/apollo4p_blue_kbr_evb/Kconfig.defconfig @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2025-2025 Ambiq Micro Inc. + +if BOARD_APOLLO4P_BLUE_KBR_EVB + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 32768 if AMBIQ_STIMER_TIMER + default 96000000 if CORTEX_M_SYSTICK + +config LOG_BACKEND_SWO_FREQ_HZ + default 1000000 + depends on LOG_BACKEND_SWO + +if BT + +config MAIN_STACK_SIZE + default 2048 + +config BT_BUF_ACL_TX_COUNT + default 14 + +config BT_BUF_EVT_RX_COUNT + default 15 + +config BT_BUF_CMD_TX_SIZE + default $(UINT8_MAX) + +config BT_BUF_EVT_RX_SIZE + default $(UINT8_MAX) + +config BT_BUF_ACL_TX_SIZE + default 251 + +config BT_BUF_ACL_RX_SIZE + default 251 + +# L2CAP SDU/PDU TX MTU +# BT_L2CAP_RX_MTU = CONFIG_BT_BUF_ACL_RX_SIZE - BT_L2CAP_HDR_SIZE +config BT_L2CAP_TX_MTU + default 247 + +endif # BT + +endif # BOARD_APOLLO4P_BLUE_KBR_EVB diff --git a/boards/ambiq/apollo4p_blue_kbr_evb/apollo4p_blue_kbr_evb-pinctrl.dtsi b/boards/ambiq/apollo4p_blue_kbr_evb/apollo4p_blue_kbr_evb-pinctrl.dtsi new file mode 100644 index 0000000000000..f2d857097c232 --- /dev/null +++ b/boards/ambiq/apollo4p_blue_kbr_evb/apollo4p_blue_kbr_evb-pinctrl.dtsi @@ -0,0 +1,174 @@ +/* + * Copyright (c) 2025 Ambiq Micro Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include "apollo4p_blue_kbr_evb_connector.dtsi" + +&pinctrl { + uart0_default: uart0_default { + group1 { + pinmux = ; + }; + group2 { + pinmux = ; + input-enable; + }; + }; + itm_default: itm_default { + group1 { + pinmux = ; + }; + }; + i2c0_default: i2c0_default { + group1 { + pinmux = , ; + drive-open-drain; + drive-strength = "0.5"; + bias-pull-up; + }; + }; + i2c1_default: i2c1_default { + group1 { + pinmux = , ; + drive-open-drain; + drive-strength = "0.5"; + bias-pull-up; + }; + }; + i2c2_default: i2c2_default { + group1 { + pinmux = , ; + drive-open-drain; + drive-strength = "0.5"; + bias-pull-up; + }; + }; + i2c3_default: i2c3_default { + group1 { + pinmux = , ; + drive-open-drain; + drive-strength = "0.5"; + bias-pull-up; + }; + }; + i2c5_default: i2c5_default { + group1 { + pinmux = , ; + drive-open-drain; + drive-strength = "0.5"; + bias-pull-up; + }; + }; + i2c6_default: i2c6_default { + group1 { + pinmux = , ; + drive-open-drain; + drive-strength = "0.5"; + bias-pull-up; + }; + }; + i2c7_default: i2c7_default { + group1 { + pinmux = , ; + drive-open-drain; + drive-strength = "0.5"; + bias-pull-up; + }; + }; + + spi0_default: spi0_default { + group1 { + pinmux = , , ; + }; + }; + spi1_default: spi1_default { + group1 { + pinmux = , , ; + }; + }; + spi2_default: spi2_default { + group1 { + pinmux = , , ; + }; + }; + spi3_default: spi3_default { + group1 { + pinmux = , , ; + }; + }; + spi4_default: spi4_default { + group1 { + pinmux = , , ; + }; + }; + spi5_default: spi5_default { + group1 { + pinmux = , , ; + }; + }; + spi6_default: spi6_default { + group1 { + pinmux = , , ; + }; + }; + spi7_default: spi7_default { + group1 { + pinmux = , , ; + }; + }; + mspi0_default: mspi0_default{ + group1 { + pinmux = , + , + ; + }; + group2 { + pinmux = ; + drive-push-pull; + drive-strength = "0.5"; + ambiq,nce-src = <0>; + }; + }; + mspi2_default: mspi2_default{ + group1 { + pinmux = , + , + ; + }; + group2 { + pinmux = ; + drive-push-pull; + drive-strength = "0.5"; + ambiq,nce-src = <32>; + }; + }; + + xo32m_default: xo32m_default { + group1 { + pinmux = ; + drive-strength = "0.1"; + }; + }; + xo32k_default: xo32k_default { + group1 { + pinmux = ; + drive-strength = "0.1"; + }; + }; + adc0_default: adc0_default{ + group1 { + pinmux = , ; + drive-strength = "0.1"; + }; + }; + pwm2_default: pwm2_default{ + group1 { + pinmux = ; + drive-open-drain; + drive-strength = "0.5"; + }; + }; +}; diff --git a/boards/ambiq/apollo4p_blue_kbr_evb/apollo4p_blue_kbr_evb.dts b/boards/ambiq/apollo4p_blue_kbr_evb/apollo4p_blue_kbr_evb.dts new file mode 100644 index 0000000000000..79736b25c9a4d --- /dev/null +++ b/boards/ambiq/apollo4p_blue_kbr_evb/apollo4p_blue_kbr_evb.dts @@ -0,0 +1,206 @@ +/dts-v1/; +#include +#include + +#include "apollo4p_blue_kbr_evb-pinctrl.dtsi" + +/ { + model = "Ambiq Apollo4 Blue Plus KBR evaluation board"; + compatible = "ambiq,apollo4p_blue_kbr_evb"; + + chosen { + zephyr,itcm = &tcm; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,uart-pipe = &uart0; + zephyr,flash-controller = &flash; + zephyr,bt-hci = &bt_hci_apollo; + }; + + aliases { + watchdog0 = &wdt0; + led0 = &led0; + led1 = &led1; + led2 = &led2; + sw0 = &button0; + sw1 = &button1; + rtc = &rtc0; + pwm-led0 = &pwm_led0; + }; + + leds { + compatible = "gpio-leds"; + led0: led_0 { + gpios = <&gpio64_95 26 GPIO_ACTIVE_LOW>; + label = "LED 0"; + }; + led1: led_1 { + gpios = <&gpio0_31 16 GPIO_ACTIVE_LOW>; + label = "LED 1"; + }; + led2: led_2 { + gpios = <&gpio64_95 27 GPIO_ACTIVE_LOW>; + label = "LED 2"; + }; + }; + + buttons { + compatible = "gpio-keys"; + polling-mode; + button0: button_0 { + gpios = <&gpio0_31 18 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "BTN0"; + zephyr,code = ; + status = "okay"; + }; + button1: button_1 { + gpios = <&gpio0_31 19 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "BTN1"; + zephyr,code = ; + status = "okay"; + }; + }; + + pwmleds: pwmleds { + compatible = "pwm-leds"; + status = "disabled"; + pwm_led0: pwm_led_0 { + pwms = <&pwm2 0 PWM_MSEC(20) PWM_POLARITY_NORMAL>; + label = "PWM_LED"; + }; + }; +}; + +&uart0 { + current-speed = <115200>; + pinctrl-0 = <&uart0_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&itm { + pinctrl-0 = <&itm_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&timer0 { + counter0: counter { + status = "disabled"; + }; +}; + +&timer2 { + pwm2: pwm { + pinctrl-0 = <&pwm2_default>; + pinctrl-names = "default"; + status = "disabled"; + }; +}; + +&rtc0 { + status = "disabled"; + clock = "XTAL"; +}; + +&wdt0 { + status = "okay"; +}; + +&iom0 { + i2c0: i2c { + pinctrl-0 = <&i2c0_default>; + pinctrl-names = "default"; + clock-frequency = ; + scl-gpios = <&gpio0_31 5 (GPIO_OPEN_DRAIN | GPIO_PULL_UP)>; + sda-gpios = <&gpio0_31 6 (GPIO_OPEN_DRAIN | GPIO_PULL_UP)>; + status = "disabled"; + }; +}; + +&iom1 { + spi1: spi { + pinctrl-0 = <&spi1_default>; + pinctrl-names = "default"; + cs-gpios = <&gpio0_31 11 GPIO_ACTIVE_LOW>; + clock-frequency = ; + status = "disabled"; + }; +}; + +&iom4 { + spi4: spi { + pinctrl-0 = <&spi4_default>; + pinctrl-names = "default"; + status = "okay"; + }; +}; + +&mspi0 { + pinctrl-0 = <&mspi0_default>; + pinctrl-names = "default"; + status = "disabled"; +}; + +&flash0 { + erase-block-size = <2048>; + write-block-size = <16>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Set 16KB of storage at the end of the 1952KB of flash */ + storage_partition: partition@1e4000 { + label = "storage"; + reg = <0x001e4000 0x4000>; + }; + }; +}; + +&stimer0 { + clk-source = <3>; +}; + +&xo32m { + pinctrl-0 = <&xo32m_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&xo32k { + pinctrl-0 = <&xo32k_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&adc0 { + pinctrl-0 = <&adc0_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +zephyr_udc0: &usb { + vddusb33-gpios = <&gpio0_31 13 (GPIO_PULL_UP)>; + vddusb0p9-gpios = <&gpio0_31 15 (GPIO_PULL_UP)>; + status = "okay"; +}; + +&gpio0_31 { + status = "okay"; +}; + +&gpio32_63 { + status = "okay"; +}; + +&gpio64_95 { + status = "okay"; +}; + +&gpio96_127 { + status = "okay"; +}; diff --git a/boards/ambiq/apollo4p_blue_kbr_evb/apollo4p_blue_kbr_evb.yaml b/boards/ambiq/apollo4p_blue_kbr_evb/apollo4p_blue_kbr_evb.yaml new file mode 100644 index 0000000000000..cb5cd5cb8e9dd --- /dev/null +++ b/boards/ambiq/apollo4p_blue_kbr_evb/apollo4p_blue_kbr_evb.yaml @@ -0,0 +1,27 @@ +identifier: apollo4p_blue_kbr_evb +name: Apollo4 Blue Plus KBR EVB +type: mcu +arch: arm +ram: 2816 +flash: 1952 +toolchain: + - zephyr + - gnuarmemb +supported: + - adc + - ble + - clock_control + - counter + - gpio + - hwinfo + - i2c + - pwm + - rtc + - spi + - uart + - usbd + - watchdog +testing: + ignore_tags: + - net +vendor: ambiq diff --git a/boards/ambiq/apollo4p_blue_kbr_evb/apollo4p_blue_kbr_evb_connector.dtsi b/boards/ambiq/apollo4p_blue_kbr_evb/apollo4p_blue_kbr_evb_connector.dtsi new file mode 100644 index 0000000000000..6cf1346198606 --- /dev/null +++ b/boards/ambiq/apollo4p_blue_kbr_evb/apollo4p_blue_kbr_evb_connector.dtsi @@ -0,0 +1,119 @@ +/* + * Copyright (c) 2023 Antmicro + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + ambiq_header: connector { + compatible = "ambiq-header"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffff80>; + gpio-map-pass-thru = <0 0x7f>; + gpio-map = <0 0 &gpio0_31 0 0>, /* IOS_SPI_SCK, IOS_I2C_SCL, MSPI2_CE0 */ + <1 0 &gpio0_31 1 0>, /* IOS_SPI_MOSI, IOS_I2C_SDA, MSPI0_CE0 */ + <2 0 &gpio0_31 2 0>, /* IOS_SPI_MISO */ + <3 0 &gpio0_31 3 0>, /* IOS_CE */ + <4 0 &gpio0_31 4 0>, /* IOS_INT, I2S0_SDIN */ + <5 0 &gpio0_31 5 0>, /* IOM0_SPI_SCK, IOM0_I2C_SCL */ + <6 0 &gpio0_31 6 0>, /* IOM0_SPI_MOSI, IOM0_I2C_SDA */ + <7 0 &gpio0_31 7 0>, /* See am_hal_pins.h file for further info */ + <8 0 &gpio0_31 8 0>, /* IOM1_SPI_SCK, IOM1_I2C_SCL */ + <9 0 &gpio0_31 9 0>, /* IOM1_SPI_MOSI, IOM1_I2C_SDA */ + <10 0 &gpio0_31 10 0>, /* IOM1_SPI_MISO */ + <11 0 &gpio0_31 11 0>, /* UART2_RX, IOM1_CS, I2S0_CLK */ + <12 0 &gpio0_31 12 0>, /* ADCSE7, UART1_TX, I2S0_DATA, I2S0_SDOUT */ + <13 0 &gpio0_31 13 0>, /* ADCSE6, UART2_TX, VDDUSB33_SWITCH */ + <14 0 &gpio0_31 14 0>, /* ADCSE5, UART1_RX, VDD18_SWITCH */ + <15 0 &gpio0_31 15 0>, /* ADCSE4, VDDUSB0P9_SWITCH */ + <16 0 &gpio0_31 16 0>, /* ADCSE3, I2S1_CLK */ + <17 0 &gpio0_31 17 0>, /* ADCSE2, UART3_RTS, I2S1_DATA */ + <18 0 &gpio0_31 18 0>, /* BUTTON0, ADCSE1, I2S1_WS */ + <19 0 &gpio0_31 19 0>, /* BUTTON1, ADCSE0, UART3_CTS, I2S1_SDIN */ + <20 0 &gpio0_31 20 0>, /* SWDCK */ + <21 0 &gpio0_31 21 0>, /* SWDIO */ + <22 0 &gpio0_31 22 0>, /* IOM7_SPI_SCK, IOM7_I2C_SCL */ + <23 0 &gpio0_31 23 0>, /* IOM7_SPI_MOSI, IOM7_I2C_SDA */ + <24 0 &gpio0_31 24 0>, /* IOM7_SPI_MISO */ + <25 0 &gpio0_31 25 0>, /* IOM2_SPI_SCK, IOM2_I2C_SCL */ + <26 0 &gpio0_31 26 0>, /* IOM2_SPI_MOSI, IOM2_I2C_SDA */ + <27 0 &gpio0_31 27 0>, /* IOM2_SPI_MISO */ + <28 0 &gpio0_31 28 0>, /* ITM_SWO */ + <29 0 &gpio0_31 29 0>, /* See am_hal_pins.h file for further info */ + <30 0 &gpio0_31 30 0>, /* LED1, IOM6_CS */ + <31 0 &gpio0_31 31 0>, /* IOM3_SPI_SCK, IOM3_I2C_SCL */ + <32 0 &gpio32_63 0 0>, /* IOM3_SPI_MOSI, IOM3_I2C_SDA */ + <33 0 &gpio32_63 1 0>, /* IOM3_SPI_MISO */ + <34 0 &gpio32_63 2 0>, /* IOM4_SPI_SCK, IOM4_I2C_SCL */ + <35 0 &gpio32_63 3 0>, /* IOM4_SPI_MOSI, IOM4_I2C_SDA */ + <36 0 &gpio32_63 4 0>, /* IOM4_SPI_MISO */ + <37 0 &gpio32_63 5 0>, /* IOM2_CS, MSPI1_D0, X16SPI_D8 */ + <38 0 &gpio32_63 6 0>, /* MSPI1_D1, X16SPI_D9 */ + <39 0 &gpio32_63 7 0>, /* MSPI1_D2, X16SPI_D10 */ + <40 0 &gpio32_63 8 0>, /* MSPI1_D3, X16SPI_D11 */ + <41 0 &gpio32_63 9 0>, /* MSPI1_D4, X16SPI_D12 */ + <42 0 &gpio32_63 10 0>, /* MSPI1_D5, X16SPI_D13 */ + <43 0 &gpio32_63 11 0>, /* IOM4_CS */ + <44 0 &gpio32_63 12 0>, /* MSPI1_D7, X16SPI_D15 */ + <45 0 &gpio32_63 13 0>, /* MSPI1_SCK, X16SPI_DQS1DM1 */ + <46 0 &gpio32_63 14 0>, /* MSPI1_DQSDM */ + <47 0 &gpio32_63 15 0>, /* COM_UART_RX, IOM5_SPI_SCK, IOM5_I2C_SCL */ + <48 0 &gpio32_63 16 0>, /* IOM5_SPI_MOSI, IOM5_I2C_SDA */ + <49 0 &gpio32_63 17 0>, /* UART1_RTS, IOM5_SPI_MISO, I2S0_WS */ + <50 0 &gpio32_63 18 0>, /* UART2_RTS, ETM_TRACECLK, PDM0_CLK */ + <51 0 &gpio32_63 19 0>, /* UART1_CTS, EMT_TRACE0, PDM0_DATA */ + <52 0 &gpio32_63 20 0>, /* UART2_CTS, MSPI0_CE1, ETM_TRACE1, PDM1_CLK */ + <53 0 &gpio32_63 21 0>, /* ETM_TRACE2, PDM1_DATA */ + <54 0 &gpio32_63 22 0>, /* ETM_TRACE3, PDM2_CLK */ + <55 0 &gpio32_63 23 0>, /* ETM_TRACECTL, PDM2_DATA */ + <56 0 &gpio32_63 24 0>, /* PDM3_CLK */ + <57 0 &gpio32_63 25 0>, /* PDM3_DATA */ + <58 0 &gpio32_63 26 0>, /* COM_UART_RTS, UART0_RTS */ + <59 0 &gpio32_63 27 0>, /* COM_UART_CTS, UART0_CTS */ + <60 0 &gpio32_63 28 0>, /* COM_UART_TX, UART0_TX, IOM5_CS */ + <61 0 &gpio32_63 29 0>, /* UART3_TX, IOM6_SPI_SCK, IOM6_I2C_SCL */ + <62 0 &gpio32_63 30 0>, /* IOM6_SPI_MOSI, IOM6_I2C_SDA */ + <63 0 &gpio32_63 31 0>, /* UART3_RX, IOM6_SPI_MISO */ + <64 0 &gpio64_95 0 0>, /* MSPI0_D0, X16SPI_D0 */ + <65 0 &gpio64_95 1 0>, /* MSPI0_D1, X16SPI_D1 */ + <66 0 &gpio64_95 2 0>, /* MSPI0_D2, X16SPI_D2 */ + <67 0 &gpio64_95 3 0>, /* MSPI0_D3, X16SPI_D3 */ + <68 0 &gpio64_95 4 0>, /* MSPI0_D4, X16SPI_D4 */ + <69 0 &gpio64_95 5 0>, /* MSPI0_D5, X16SPI_D5 */ + <70 0 &gpio64_95 6 0>, /* MSPI0_D6, X16SPI_D6 */ + <71 0 &gpio64_95 7 0>, /* MSPI0_D7, X16SPI_D7 */ + <72 0 &gpio64_95 8 0>, /* IOM0_CS, MSPI0_SCK, X16SPI_SCK */ + <73 0 &gpio64_95 9 0>, /* MSPI0_DQSDM, X16SPI_DQSDM */ + <74 0 &gpio64_95 10 0>, /* MSPI2_D0 */ + <75 0 &gpio64_95 11 0>, /* MSPI2_D1 */ + <76 0 &gpio64_95 12 0>, /* MSPI2_D2 */ + <77 0 &gpio64_95 13 0>, /* MSPI2_D3 */ + <78 0 &gpio64_95 14 0>, /* MSPI2_D4 */ + <79 0 &gpio64_95 15 0>, /* MSPI2_D5, SDIF_DAT4 */ + <80 0 &gpio64_95 16 0>, /* MSPI2_D6, SDIF_DAT5 */ + <81 0 &gpio64_95 17 0>, /* MSPI2_D7, SDIF_DAT6 */ + <82 0 &gpio64_95 18 0>, /* MSPI2_D8, SDIF_DAT7 */ + <83 0 &gpio64_95 19 0>, /* MSPI2_DQSDM, SDIF_CMD */ + <84 0 &gpio64_95 20 0>, /* SDIF_DAT0 */ + <85 0 &gpio64_95 21 0>, /* IOM3_CS, SDIF_DAT1 */ + <86 0 &gpio64_95 22 0>, /* MSPI2_CE1, SDIF_DAT2 */ + <87 0 &gpio64_95 23 0>, /* SDIF_DAT3 */ + <88 0 &gpio64_95 24 0>, /* IOM7_CS, SDIF_CLKOUT */ + <89 0 &gpio64_95 25 0>, /* MSPI1_CE0, X16SPI_CE0, X16SPI_CE1 */ + <90 0 &gpio64_95 26 0>, /* LED0 */ + <91 0 &gpio64_95 27 0>, /* LED2 */ + <92 0 &gpio64_95 28 0>, /* See am_hal_pins.h file for further info */ + <93 0 &gpio64_95 29 0>, /* See am_hal_pins.h file for further info */ + <94 0 &gpio64_95 30 0>, /* See am_hal_pins.h file for further info */ + <95 0 &gpio64_95 31 0>, /* See am_hal_pins.h file for further info */ + <96 0 &gpio96_127 0 0>, /* See am_hal_pins.h file for further info */ + <97 0 &gpio96_127 1 0>, /* See am_hal_pins.h file for further info */ + <98 0 &gpio96_127 2 0>, /* See am_hal_pins.h file for further info */ + <99 0 &gpio96_127 3 0>, /* See am_hal_pins.h file for further info */ + <100 0 &gpio96_127 4 0>, /* See am_hal_pins.h file for further info */ + <101 0 &gpio96_127 5 0>, /* See am_hal_pins.h file for further info */ + <102 0 &gpio96_127 6 0>, /* See am_hal_pins.h file for further info */ + <103 0 &gpio96_127 7 0>, /* See am_hal_pins.h file for further info */ + <104 0 &gpio96_127 8 0>; /* See am_hal_pins.h file for further info */ + }; +}; diff --git a/boards/ambiq/apollo4p_blue_kbr_evb/apollo4p_blue_kbr_evb_defconfig b/boards/ambiq/apollo4p_blue_kbr_evb/apollo4p_blue_kbr_evb_defconfig new file mode 100644 index 0000000000000..9ac87e65313cd --- /dev/null +++ b/boards/ambiq/apollo4p_blue_kbr_evb/apollo4p_blue_kbr_evb_defconfig @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2025 Ambiq Micro Inc. + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y diff --git a/boards/ambiq/apollo4p_blue_kbr_evb/board.cmake b/boards/ambiq/apollo4p_blue_kbr_evb/board.cmake new file mode 100644 index 0000000000000..9351b4fde964c --- /dev/null +++ b/boards/ambiq/apollo4p_blue_kbr_evb/board.cmake @@ -0,0 +1,6 @@ +# Copyright (c) 2025 Ambiq Micro Inc. +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(jlink "--device=AMAP42KP-KBR" "--iface=swd" "--speed=1000") + +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/ambiq/apollo4p_blue_kbr_evb/board.yml b/boards/ambiq/apollo4p_blue_kbr_evb/board.yml new file mode 100644 index 0000000000000..a7393cfd4cb52 --- /dev/null +++ b/boards/ambiq/apollo4p_blue_kbr_evb/board.yml @@ -0,0 +1,6 @@ +board: + name: apollo4p_blue_kbr_evb + full_name: Apollo4 Blue Plus KBR EVB + vendor: ambiq + socs: + - name: apollo4p_blue diff --git a/boards/ambiq/apollo4p_blue_kbr_evb/doc/apollo4-blue-plus-kxr-soc-eval-board.jpg b/boards/ambiq/apollo4p_blue_kbr_evb/doc/apollo4-blue-plus-kxr-soc-eval-board.jpg new file mode 100644 index 0000000000000..c1825eb4c06f7 Binary files /dev/null and b/boards/ambiq/apollo4p_blue_kbr_evb/doc/apollo4-blue-plus-kxr-soc-eval-board.jpg differ diff --git a/boards/ambiq/apollo4p_blue_kbr_evb/doc/index.rst b/boards/ambiq/apollo4p_blue_kbr_evb/doc/index.rst new file mode 100644 index 0000000000000..1b5f9fa90f4b1 --- /dev/null +++ b/boards/ambiq/apollo4p_blue_kbr_evb/doc/index.rst @@ -0,0 +1,72 @@ +.. zephyr:board:: apollo4p_blue_kbr_evb + +Apollo4 Blue Plus KBR EVB is a board by Ambiq featuring their ultra-low power Apollo4 Blue Plus SoC. + +Hardware +******** + +- Apollo4 Blue Plus SoC with up to 192 MHz operating frequency +- ARM® Cortex® M4F core +- 64 kB 2-way Associative/Direct-Mapped Cache per core +- Up to 2 MB of non-volatile memory (NVM) for code/data +- Up to 2.75 MB of low leakage / low power RAM for code/data +- 384 kB Tightly Coupled RAM +- 384 kB Extended RAM +- Bluetooth 5.1 Low Energy + +For more information about the Apollo4 Blue Plus SoC and Apollo4 Blue Plus KXR EVB board: + +- `Apollo4 Blue Plus Website`_ +- `Apollo4 Blue Plus Datasheet`_ + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +Programming and Debugging +========================= + +.. zephyr:board-supported-runners:: + +Flashing an application +----------------------- + +Connect your device to your host computer using the JLINK USB port. +The sample application :zephyr:code-sample:`hello_world` is used for this example. +Build the Zephyr kernel and application, then flash it to the device: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: apollo4p_blue_kbr_evb + :goals: flash + +.. note:: + ``west flash`` requires `SEGGER J-Link software`_ and `pylink`_ Python module + to be installed on you host computer. + +Open a serial terminal (minicom, putty, etc.) with the following settings: + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Reset the board and you should be able to see on the corresponding Serial Port +the following message: + +.. code-block:: console + + Hello World! apollo4p_blue_kbr_evb + +.. _Apollo4 Blue Plus Website: + https://ambiq.com/apollo4-blue-plus/ + +.. _Apollo4 Blue Plus Datasheet: + https://contentportal.ambiq.com/documents/20123/388410/Apollo4-Blue-Plus-SoC-Datasheet.pdf + +.. _SEGGER J-Link software: + https://www.segger.com/downloads/jlink + +.. _pylink: + https://github.com/Square/pylink diff --git a/boards/ambiq/apollo4p_blue_kxr_evb/apollo4p_blue_kxr_evb-pinctrl.dtsi b/boards/ambiq/apollo4p_blue_kxr_evb/apollo4p_blue_kxr_evb-pinctrl.dtsi index 6e8d473c3f2b7..2254932d04246 100644 --- a/boards/ambiq/apollo4p_blue_kxr_evb/apollo4p_blue_kxr_evb-pinctrl.dtsi +++ b/boards/ambiq/apollo4p_blue_kxr_evb/apollo4p_blue_kxr_evb-pinctrl.dtsi @@ -5,6 +5,7 @@ */ #include +#include "apollo4p_blue_kxr_evb_connector.dtsi" &pinctrl { uart0_default: uart0_default { diff --git a/boards/ambiq/apollo4p_blue_kxr_evb/apollo4p_blue_kxr_evb_connector.dtsi b/boards/ambiq/apollo4p_blue_kxr_evb/apollo4p_blue_kxr_evb_connector.dtsi new file mode 100644 index 0000000000000..de2221ed781c3 --- /dev/null +++ b/boards/ambiq/apollo4p_blue_kxr_evb/apollo4p_blue_kxr_evb_connector.dtsi @@ -0,0 +1,122 @@ +/* + * Copyright (c) 2023 Antmicro + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + ambiq_header: connector { + compatible = "ambiq-header"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffff80>; + gpio-map-pass-thru = <0 0x7f>; + gpio-map = <0 0 &gpio0_31 0 0>, /* IOS_SPI_SCK, IOS_I2C_SCL, UART1_TX */ + <1 0 &gpio0_31 1 0>, /* IOS_SPI_MOSI, IOS_I2C_SDA, MSPI0_CE0 */ + <2 0 &gpio0_31 2 0>, /* IOS_SPI_MISO */ + <3 0 &gpio0_31 3 0>, /* IOS_CE */ + <4 0 &gpio0_31 4 0>, /* IOS_INT */ + <5 0 &gpio0_31 5 0>, /* IOM0_SPI_SCK, IOM0_I2C_SCL */ + <6 0 &gpio0_31 6 0>, /* IOM0_SPI_MOSI, IOM0_I2C_SDA */ + <7 0 &gpio0_31 7 0>, /* See am_hal_pins.h file for further info */ + <8 0 &gpio0_31 8 0>, /* IOM1_SPI_SCK, IOM1_I2C_SCL */ + <9 0 &gpio0_31 9 0>, /* IOM1_SPI_MOSI, IOM1_I2C_SDA */ + <10 0 &gpio0_31 10 0>, /* IOM1_SPI_MISO */ + <11 0 &gpio0_31 11 0>, /* UART2_RX, IOM1_CS, I2S0_CLK */ + <12 0 &gpio0_31 12 0>, /* ADCSE7, COM_UART_TX, I2S0_DATA, I2S0_SDOUT */ + <13 0 &gpio0_31 13 0>, /* ADCSE6, UART2_TX, I2S0_WS, VDDUSB33_SWITCH */ + <14 0 &gpio0_31 14 0>, /* ADCSE5, UART1_RX, I2S0_SDIN, VDD18_SWITCH */ + <15 0 &gpio0_31 15 0>, /* ADCSE4, VDDUSB0P9_SWITCH */ + <16 0 &gpio0_31 16 0>, /* LED0 */ + <17 0 &gpio0_31 17 0>, /* BUTTON0 */ + <18 0 &gpio0_31 18 0>, /* ADCSE1, COM_UART_CTS */ + <19 0 &gpio0_31 19 0>, /* BUTTON1, ADCSE0, UART3_CTS, I2S1_SDIN */ + <20 0 &gpio0_31 20 0>, /* SWDCK */ + <21 0 &gpio0_31 21 0>, /* SWDIO */ + <22 0 &gpio0_31 22 0>, /* IOM7_SPI_SCK, IOM7_I2C_SCL */ + <23 0 &gpio0_31 23 0>, /* IOM7_SPI_MOSI, IOM7_I2C_SDA */ + <24 0 &gpio0_31 24 0>, /* IOM7_SPI_MISO */ + <25 0 &gpio0_31 25 0>, /* IOM2_SPI_SCK, IOM2_I2C_SCL */ + <26 0 &gpio0_31 26 0>, /* IOM2_SPI_MOSI, IOM2_I2C_SDA */ + <27 0 &gpio0_31 27 0>, /* IOM2_SPI_MISO */ + <28 0 &gpio0_31 28 0>, /* ITM_SWO */ + <29 0 &gpio0_31 29 0>, /* See am_hal_pins.h file for further info */ + <30 0 &gpio0_31 30 0>, /* LED1, IOM6_CS */ + <31 0 &gpio0_31 31 0>, /* IOM3_SPI_SCK, IOM3_I2C_SCL */ + <32 0 &gpio32_63 0 0>, /* IOM3_SPI_MOSI, IOM3_I2C_SDA */ + <33 0 &gpio32_63 1 0>, /* IOM3_SPI_MISO */ + <34 0 &gpio32_63 2 0>, /* IOM4_SPI_SCK, IOM4_I2C_SCL */ + <35 0 &gpio32_63 3 0>, /* IOM4_SPI_MOSI, IOM4_I2C_SDA */ + <36 0 &gpio32_63 4 0>, /* IOM4_SPI_MISO */ + <37 0 &gpio32_63 5 0>, /* IOM2_CS, MSPI1_D0, X16SPI_D8 */ + <38 0 &gpio32_63 6 0>, /* MSPI1_D1, X16SPI_D9 */ + <39 0 &gpio32_63 7 0>, /* MSPI1_D2, X16SPI_D10 */ + <40 0 &gpio32_63 8 0>, /* MSPI1_D3, X16SPI_D11 */ + <41 0 &gpio32_63 9 0>, /* MSPI1_D4, X16SPI_D12 */ + <42 0 &gpio32_63 10 0>, /* MSPI1_D5, X16SPI_D13 */ + <43 0 &gpio32_63 11 0>, /* MSPI1_D6, X16SPI_D14 */ + <44 0 &gpio32_63 12 0>, /* MSPI1_D7, X16SPI_D15 */ + <45 0 &gpio32_63 13 0>, /* MSPI1_SCK, X16SPI_DQS1DM1 */ + <46 0 &gpio32_63 14 0>, /* MSPI1_DQSDM */ + <47 0 &gpio32_63 15 0>, /* COM_UART_RX, IOM5_SPI_SCK, IOM5_I2C_SCL */ + <48 0 &gpio32_63 16 0>, /* IOM5_SPI_MOSI, IOM5_I2C_SDA */ + <49 0 &gpio32_63 17 0>, /* UART1_RTS, IOM5_SPI_MISO */ + <50 0 &gpio32_63 18 0>, /* UART2_RTS, ETM_TRACECLK, PDM0_CLK */ + <51 0 &gpio32_63 19 0>, /* UART1_CTS, EMT_TRACE0, PDM0_DATA */ + <52 0 &gpio32_63 20 0>, /* UART2_CTS, MSPI0_CE1, ETM_TRACE1, PDM1_CLK */ + <53 0 &gpio32_63 21 0>, /* ETM_TRACE2, PDM1_DATA */ + <54 0 &gpio32_63 22 0>, /* ETM_TRACE3, PDM2_CLK */ + <55 0 &gpio32_63 23 0>, /* ETM_TRACECTL, PDM2_DATA */ + <56 0 &gpio32_63 24 0>, /* PDM3_CLK */ + <57 0 &gpio32_63 25 0>, /* PDM3_DATA */ + <58 0 &gpio32_63 26 0>, /* COM_UART_RTS, UART0_RTS */ + <59 0 &gpio32_63 27 0>, /* COM_UART_CTS, UART0_CTS */ + <60 0 &gpio32_63 28 0>, /* COM_UART_TX, UART0_TX, IOM5_CS */ + <61 0 &gpio32_63 29 0>, /* UART3_TX, IOM6_SPI_SCK, IOM6_I2C_SCL */ + <62 0 &gpio32_63 30 0>, /* IOM6_SPI_MOSI, IOM6_I2C_SDA */ + <63 0 &gpio32_63 31 0>, /* UART3_RX, IOM6_SPI_MISO */ + <64 0 &gpio64_95 0 0>, /* MSPI0_D0, X16SPI_D0 */ + <65 0 &gpio64_95 1 0>, /* MSPI0_D1, X16SPI_D1 */ + <66 0 &gpio64_95 2 0>, /* MSPI0_D2, X16SPI_D2 */ + <67 0 &gpio64_95 3 0>, /* MSPI0_D3, X16SPI_D3 */ + <68 0 &gpio64_95 4 0>, /* MSPI0_D4, X16SPI_D4 */ + <69 0 &gpio64_95 5 0>, /* MSPI0_D5, X16SPI_D5 */ + <70 0 &gpio64_95 6 0>, /* MSPI0_D6, X16SPI_D6 */ + <71 0 &gpio64_95 7 0>, /* MSPI0_D7, X16SPI_D7 */ + <72 0 &gpio64_95 8 0>, /* IOM0_CS, MSPI0_SCK, X16SPI_SCK */ + <73 0 &gpio64_95 9 0>, /* MSPI0_DQSDM, X16SPI_DQSDM */ + <74 0 &gpio64_95 10 0>, /* MSPI2_D0 */ + <75 0 &gpio64_95 11 0>, /* MSPI2_D1 */ + <76 0 &gpio64_95 12 0>, /* MSPI2_D2 */ + <77 0 &gpio64_95 13 0>, /* MSPI2_D3 */ + <78 0 &gpio64_95 14 0>, /* MSPI2_D4 */ + <79 0 &gpio64_95 15 0>, /* IOM4_CS, MSPI2_D5, SDIF_DAT4 */ + <80 0 &gpio64_95 16 0>, /* MSPI2_D6, SDIF_DAT5 */ + <81 0 &gpio64_95 17 0>, /* MSPI2_D7, SDIF_DAT6 */ + <82 0 &gpio64_95 18 0>, /* MSPI2_D8, SDIF_DAT7 */ + <83 0 &gpio64_95 19 0>, /* MSPI2_DQSDM, SDIF_CMD */ + <84 0 &gpio64_95 20 0>, /* SDIF_DAT0 */ + <85 0 &gpio64_95 21 0>, /* IOM3_CS, SDIF_DAT1 */ + <86 0 &gpio64_95 22 0>, /* MSPI2_CE1, SDIF_DAT2 */ + <87 0 &gpio64_95 23 0>, /* SDIF_DAT3 */ + <88 0 &gpio64_95 24 0>, /* IOM7_CS, SDIF_CLKOUT */ + <89 0 &gpio64_95 25 0>, /* MSPI1_CE0, X16SPI_CE0, X16SPI_CE1 */ + <90 0 &gpio64_95 26 0>, /* LED0 */ + <91 0 &gpio64_95 27 0>, /* LED2 */ + <92 0 &gpio64_95 28 0>, /* See am_hal_pins.h file for further info */ + <93 0 &gpio64_95 29 0>, /* See am_hal_pins.h file for further info */ + <94 0 &gpio64_95 30 0>, /* See am_hal_pins.h file for further info */ + <95 0 &gpio64_95 31 0>, /* See am_hal_pins.h file for further info */ + <96 0 &gpio96_127 0 0>, /* See am_hal_pins.h file for further info */ + <97 0 &gpio96_127 1 0>, /* See am_hal_pins.h file for further info */ + <98 0 &gpio96_127 2 0>, /* See am_hal_pins.h file for further info */ + <99 0 &gpio96_127 3 0>, /* See am_hal_pins.h file for further info */ + <100 0 &gpio96_127 4 0>, /* See am_hal_pins.h file for further info */ + <101 0 &gpio96_127 5 0>, /* See am_hal_pins.h file for further info */ + <102 0 &gpio96_127 6 0>, /* See am_hal_pins.h file for further info */ + <103 0 &gpio96_127 7 0>, /* See am_hal_pins.h file for further info */ + <104 0 &gpio96_127 8 0>; /* See am_hal_pins.h file for further info */ + }; +}; + +ambiq_spi1: &iom1 {}; +mspi_aps256n: &mspi0 {}; diff --git a/boards/ambiq/apollo4p_blue_kxr_evb/doc/index.rst b/boards/ambiq/apollo4p_blue_kxr_evb/doc/index.rst index b6e891ef53f3b..9f76cf5fef7ec 100644 --- a/boards/ambiq/apollo4p_blue_kxr_evb/doc/index.rst +++ b/boards/ambiq/apollo4p_blue_kxr_evb/doc/index.rst @@ -5,7 +5,7 @@ Apollo4 Blue Plus KXR EVB is a board by Ambiq featuring their ultra-low power Ap Hardware ******** -- Apollo4 Blue Plus SoC with upto 192 MHz operating frequency +- Apollo4 Blue Plus SoC with up to 192 MHz operating frequency - ARM® Cortex® M4F core - 64 kB 2-way Associative/Direct-Mapped Cache per core - Up to 2 MB of non-volatile memory (NVM) for code/data @@ -14,11 +14,11 @@ Hardware - 384 kB Extended RAM - Bluetooth 5.1 Low Energy -For more information about the Apollo4 Blue Plus SoC and Apollo4 Blue Plus KXR EVB board: +For more information about the Apollo4 Blue Plus SoC and Apollo4 Blue Plus KBR EVB board: - `Apollo4 Blue Plus Website`_ - `Apollo4 Blue Plus Datasheet`_ -- `Apollo4 Blue Plus KXR EVB Website`_ +- `Apollo4 Blue Plus KBR EVB Website`_ Supported Features ================== @@ -39,7 +39,7 @@ Build the Zephyr kernel and application, then flash it to the device: .. zephyr-app-commands:: :zephyr-app: samples/hello_world - :board: apollo4p_blue_kxr_evb + :board: apollo4p_blue_kbr_evb :goals: flash .. note:: @@ -66,9 +66,6 @@ the following message: .. _Apollo4 Blue Plus Datasheet: https://contentportal.ambiq.com/documents/20123/388410/Apollo4-Blue-Plus-SoC-Datasheet.pdf -.. _Apollo4 Blue Plus KXR EVB Website: - https://www.ambiq.top/en/apollo4-blue-plus-kxr-soc-eval-board - .. _SEGGER J-Link software: https://www.segger.com/downloads/jlink diff --git a/boards/ambiq/apollo4p_evb/apollo4p_evb_connector.dtsi b/boards/ambiq/apollo4p_evb/apollo4p_evb_connector.dtsi index 9236c0971bcbc..72afcafedb93a 100644 --- a/boards/ambiq/apollo4p_evb/apollo4p_evb_connector.dtsi +++ b/boards/ambiq/apollo4p_evb/apollo4p_evb_connector.dtsi @@ -30,8 +30,8 @@ <17 0 &gpio0_31 17 0>, /* ADCSE2, UART3_RTS, I2S1_DATA */ <18 0 &gpio0_31 18 0>, /* BUTTON0, ADCSE1, I2S1_WS */ <19 0 &gpio0_31 19 0>, /* BUTTON1, ADCSE0, UART3_CTS, I2S1_SDIN */ - <20 0 &gpio0_31 19 0>, /* SWDCK */ - <21 0 &gpio0_31 19 0>, /* SWDIO */ + <20 0 &gpio0_31 20 0>, /* SWDCK */ + <21 0 &gpio0_31 21 0>, /* SWDIO */ <22 0 &gpio0_31 22 0>, /* IOM7_SPI_SCK, IOM7_I2C_SCL */ <23 0 &gpio0_31 23 0>, /* IOM7_SPI_MOSI, IOM7_I2C_SDA */ <24 0 &gpio0_31 24 0>, /* IOM7_SPI_MISO */ @@ -107,7 +107,7 @@ <94 0 &gpio64_95 30 0>, /* See am_hal_pins.h file for further info */ <95 0 &gpio64_95 31 0>, /* See am_hal_pins.h file for further info */ <96 0 &gpio96_127 0 0>, /* See am_hal_pins.h file for further info */ - <97 0 &gpio96_127 1 0>, /* See am_hal_pins.h file for further info */ + <97 0 &gpio96_127 1 0>, /* LED2 */ <98 0 &gpio96_127 2 0>, /* See am_hal_pins.h file for further info */ <99 0 &gpio96_127 3 0>, /* See am_hal_pins.h file for further info */ <100 0 &gpio96_127 4 0>, /* See am_hal_pins.h file for further info */ diff --git a/include/zephyr/dt-bindings/pinctrl/ambiq-apollo4-pinctrl.h b/include/zephyr/dt-bindings/pinctrl/ambiq-apollo4-pinctrl.h index 522b5155ab71d..bffb24a8d29c0 100644 --- a/include/zephyr/dt-bindings/pinctrl/ambiq-apollo4-pinctrl.h +++ b/include/zephyr/dt-bindings/pinctrl/ambiq-apollo4-pinctrl.h @@ -57,16 +57,23 @@ #define GPIO_P3 APOLLO4_PINMUX(3, 3) #define UART2RX_P3 APOLLO4_PINMUX(3, 4) #define UART3RX_P3 APOLLO4_PINMUX(3, 5) +#if APOLLO4P_BLUE_KBR_EVB +#undef UART3RX_P3 +#define UART3RX_P3 APOLLO4_PINMUX(3, 4) +#endif +#define UART3TX_P3 APOLLO4_PINMUX(3, 5) #define CT3_P3 APOLLO4_PINMUX(3, 6) #define NCE3_P3 APOLLO4_PINMUX(3, 7) #define OBSBUS3_P3 APOLLO4_PINMUX(3, 8) #define FPIO_P3 APOLLO4_PINMUX(3, 11) #define SCANIN5_P3 APOLLO4_PINMUX(3, 15) +#define SWTRACE1_P4 APOLLO4_PINMUX(4, 0) #define SWTRACE3_P4 APOLLO4_PINMUX(4, 0) #define SLINT_P4 APOLLO4_PINMUX(4, 1) #define XT32KHZ_P4 APOLLO4_PINMUX(4, 2) #define GPIO_P4 APOLLO4_PINMUX(4, 3) #define UART0RTS_P4 APOLLO4_PINMUX(4, 4) +#define UART2RTS_P4 APOLLO4_PINMUX(4, 4) #define UART1RTS_P4 APOLLO4_PINMUX(4, 5) #define CT4_P4 APOLLO4_PINMUX(4, 6) #define NCE4_P4 APOLLO4_PINMUX(4, 7) @@ -818,6 +825,7 @@ #define VCMPO_P72 APOLLO4_PINMUX(72, 9) #define FPIO_P72 APOLLO4_PINMUX(72, 11) #define MSPI0_9_P73 APOLLO4_PINMUX(73, 0) +#define CLKOUT_32M_P73 APOLLO4_PINMUX(73, 1) #define SWTRACE3_P73 APOLLO4_PINMUX(73, 2) #define GPIO_P73 APOLLO4_PINMUX(73, 3) #define UART2TX_P73 APOLLO4_PINMUX(73, 4) diff --git a/samples/basic/blinky_pwm/boards/apollo4p_blue_kbr_evb.overlay b/samples/basic/blinky_pwm/boards/apollo4p_blue_kbr_evb.overlay new file mode 100644 index 0000000000000..50c4fe189969c --- /dev/null +++ b/samples/basic/blinky_pwm/boards/apollo4p_blue_kbr_evb.overlay @@ -0,0 +1,13 @@ +/* + * Copyright (c) 2025 Ambiq + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&pwmleds { + status = "okay"; +}; + +&pwm2 { + status = "okay"; +}; diff --git a/samples/drivers/counter/alarm/boards/apollo4p_blue_kbr_evb.overlay b/samples/drivers/counter/alarm/boards/apollo4p_blue_kbr_evb.overlay new file mode 100644 index 0000000000000..398a8b3524260 --- /dev/null +++ b/samples/drivers/counter/alarm/boards/apollo4p_blue_kbr_evb.overlay @@ -0,0 +1,5 @@ +&timer0 { + counter0: counter { + status = "okay"; + }; +}; diff --git a/samples/drivers/led/pwm/boards/apollo4p_blue_kbr_evb.overlay b/samples/drivers/led/pwm/boards/apollo4p_blue_kbr_evb.overlay new file mode 100644 index 0000000000000..1663aaa96f3e6 --- /dev/null +++ b/samples/drivers/led/pwm/boards/apollo4p_blue_kbr_evb.overlay @@ -0,0 +1,21 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + * + * Copyright (c) 2025 Ambiq + */ + +/ { + /* do not define the led on the pa5 but a pwmleds */ + leds { + status = "disabled"; + }; +}; + +&pwmleds { + /* NOTE: enable here because it is disabled by default */ + status = "okay"; +}; + +&pwm2 { + status = "okay"; +}; diff --git a/tests/drivers/adc/adc_api/boards/apollo4p_blue_kbr_evb.overlay b/tests/drivers/adc/adc_api/boards/apollo4p_blue_kbr_evb.overlay new file mode 100644 index 0000000000000..5676f0c47265f --- /dev/null +++ b/tests/drivers/adc/adc_api/boards/apollo4p_blue_kbr_evb.overlay @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2024 Ambiq Micro Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ +/ { + zephyr,user { + io-channels = <&adc0 4>, <&adc0 7>; + }; +}; + +&adc0 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + channel@4 { + reg = <4>; + zephyr,gain = "ADC_GAIN_1"; + zephyr,reference = "ADC_REF_INTERNAL"; + zephyr,acquisition-time = ; + zephyr,resolution = <12>; + }; + + channel@7 { + reg = <7>; + zephyr,gain = "ADC_GAIN_1"; + zephyr,reference = "ADC_REF_INTERNAL"; + zephyr,acquisition-time = ; + zephyr,resolution = <12>; + }; +}; diff --git a/tests/drivers/counter/counter_basic_api/boards/apollo4p_blue_kbr_evb.overlay b/tests/drivers/counter/counter_basic_api/boards/apollo4p_blue_kbr_evb.overlay new file mode 100644 index 0000000000000..398a8b3524260 --- /dev/null +++ b/tests/drivers/counter/counter_basic_api/boards/apollo4p_blue_kbr_evb.overlay @@ -0,0 +1,5 @@ +&timer0 { + counter0: counter { + status = "okay"; + }; +}; diff --git a/tests/drivers/gpio/gpio_basic_api/boards/apollo4p_blue_kbr_evb.overlay b/tests/drivers/gpio/gpio_basic_api/boards/apollo4p_blue_kbr_evb.overlay new file mode 100644 index 0000000000000..0e252d3a578ad --- /dev/null +++ b/tests/drivers/gpio/gpio_basic_api/boards/apollo4p_blue_kbr_evb.overlay @@ -0,0 +1,13 @@ +/* + * Copyright (c) 2025 Ambiq Micro Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + resources { + compatible = "test-gpio-basic-api"; + out-gpios = <&ambiq_header 12 0>; + in-gpios = <&ambiq_header 13 0>; + }; +}; diff --git a/tests/drivers/pwm/pwm_api/boards/apollo4p_blue_kbr_evb.overlay b/tests/drivers/pwm/pwm_api/boards/apollo4p_blue_kbr_evb.overlay new file mode 100644 index 0000000000000..b2275d35fc08c --- /dev/null +++ b/tests/drivers/pwm/pwm_api/boards/apollo4p_blue_kbr_evb.overlay @@ -0,0 +1,15 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + * + * Copyright (c) 2025 Ambiq + */ + +/ { + aliases { + pwm-0 = &pwm2; + }; +}; + +&pwm2 { + status = "okay"; +}; diff --git a/tests/drivers/rtc/rtc_api/boards/apollo4p_blue_kbr_evb.conf b/tests/drivers/rtc/rtc_api/boards/apollo4p_blue_kbr_evb.conf new file mode 100644 index 0000000000000..7a77183e0a22e --- /dev/null +++ b/tests/drivers/rtc/rtc_api/boards/apollo4p_blue_kbr_evb.conf @@ -0,0 +1,5 @@ +# Copyright (c) 2025, Ambiq Micro Inc. +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_RTC_ALARM=y +CONFIG_TEST_RTC_ALARM_TIME_MASK=79 diff --git a/tests/drivers/rtc/rtc_api/boards/apollo4p_blue_kbr_evb.overlay b/tests/drivers/rtc/rtc_api/boards/apollo4p_blue_kbr_evb.overlay new file mode 100644 index 0000000000000..628ce2c01e61b --- /dev/null +++ b/tests/drivers/rtc/rtc_api/boards/apollo4p_blue_kbr_evb.overlay @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2025 Ambiq Micro Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + aliases { + rtc = &rtc0; + }; +}; + +&rtc0 { + status = "okay"; +}; diff --git a/tests/drivers/rtc/rtc_api/boards/apollo4p_blue_kxr_evb.overlay b/tests/drivers/rtc/rtc_api/boards/apollo4p_blue_kxr_evb.overlay new file mode 100644 index 0000000000000..628ce2c01e61b --- /dev/null +++ b/tests/drivers/rtc/rtc_api/boards/apollo4p_blue_kxr_evb.overlay @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2025 Ambiq Micro Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + aliases { + rtc = &rtc0; + }; +}; + +&rtc0 { + status = "okay"; +}; diff --git a/west.yml b/west.yml index 852bfa0d7854e..011abc23c7938 100644 --- a/west.yml +++ b/west.yml @@ -40,7 +40,7 @@ manifest: - name: ambiqhal_ambiq remote: github_ambiqmicro path: modules/hal/ambiq - revision: 016bf096b862378e5091dce6e3ab0a71908ec934 + revision: 9647b405e55e2a85184a6013ec3de84d407446f9 groups: - hal - name: babblesim_base