Skip to content

Commit 0107c93

Browse files
harrisonGPUharrisonGPU
authored
[DAG] canCreateUndefOrPoison – mark fneg/fadd/fsub/fmul/fdiv/frem as not poison generating (llvm#142345)
After revisiting the LLVM Language Reference Manual, it is confirmed that plain floating-point operations (`fneg`, `fadd`, `fsub`, `fmul`, `fdiv`, and `frem`) propagate poison but do not inherently create new poison values. Thus, `SelectionDAG::canCreateUndefOrPoison` should return `false` for these operations by default. Poison generation in FP instructions occurs only when specific fast-math flags (`nnan`, `ninf`, or the collective fast) are present, as these flags explicitly convert NaN or Inf results into poison. References: - [`fneg` instruction documentation](https://llvm.org/docs/LangRef.html#fneg-instruction) - [`fadd` instruction documentation](https://llvm.org/docs/LangRef.html#fadd-instruction) - [`fsub` instruction documentation](https://llvm.org/docs/LangRef.html#fsub-instruction) - [`fmul` instruction documentation](https://llvm.org/docs/LangRef.html#fmul-instruction) - [`fdiv` instruction documentation](https://llvm.org/docs/LangRef.html#fdiv-instruction) - [`frem` instruction documentation](https://llvm.org/docs/LangRef.html#frem-instruction) - [Fast-Math Flags documentation](https://llvm.org/docs/LangRef.html#fast-math-flags)
1 parent 05547fc commit 0107c93

File tree

2 files changed

+206
-0
lines changed

2 files changed

+206
-0
lines changed

‎llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp‎

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -5639,6 +5639,12 @@ bool SelectionDAG::canCreateUndefOrPoison(SDValue Op, const APInt &DemandedElts,
56395639
case ISD::ADD:
56405640
case ISD::SUB:
56415641
case ISD::MUL:
5642+
case ISD::FNEG:
5643+
case ISD::FADD:
5644+
case ISD::FSUB:
5645+
case ISD::FMUL:
5646+
case ISD::FDIV:
5647+
case ISD::FREM:
56425648
// No poison except from flags (which is handled above)
56435649
return false;
56445650

‎llvm/test/CodeGen/AMDGPU/freeze-binary.ll‎

Lines changed: 200 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,200 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
2+
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 < %s | FileCheck %s
3+
4+
define float @freeze_fneg(float %input) nounwind {
5+
; CHECK-LABEL: freeze_fneg:
6+
; CHECK: ; %bb.0:
7+
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
8+
; CHECK-NEXT: s_setpc_b64 s[30:31]
9+
%x = fneg reassoc nsz arcp contract afn float %input
10+
%y = freeze float %x
11+
%z = fneg reassoc nsz arcp contract afn float %y
12+
ret float %z
13+
}
14+
15+
define float @freeze_fadd(float %input) nounwind {
16+
; CHECK-LABEL: freeze_fadd:
17+
; CHECK: ; %bb.0:
18+
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
19+
; CHECK-NEXT: v_add_f32_e32 v0, 2.0, v0
20+
; CHECK-NEXT: s_setpc_b64 s[30:31]
21+
%x = fadd reassoc nsz arcp contract afn float %input, 1.000000e+00
22+
%y = freeze float %x
23+
%z = fadd reassoc nsz arcp contract afn float %y, 1.000000e+00
24+
ret float %z
25+
}
26+
27+
define <4 x float> @freeze_fadd_vec(<4 x float> %input) nounwind {
28+
; CHECK-LABEL: freeze_fadd_vec:
29+
; CHECK: ; %bb.0:
30+
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
31+
; CHECK-NEXT: v_dual_add_f32 v0, 0x40a00000, v0 :: v_dual_add_f32 v1, 0x40a00000, v1
32+
; CHECK-NEXT: v_dual_add_f32 v2, 0x40a00000, v2 :: v_dual_add_f32 v3, 0x40a00000, v3
33+
; CHECK-NEXT: s_setpc_b64 s[30:31]
34+
%x = fadd reassoc nsz arcp contract afn <4 x float> %input, <float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+00>
35+
%y = freeze <4 x float> %x
36+
%z = fadd reassoc nsz arcp contract afn <4 x float> %y, <float 4.000000e+00, float 3.000000e+00, float 2.000000e+00, float 1.000000e+00>
37+
ret <4 x float> %z
38+
}
39+
40+
define float @freeze_fsub(float %input) nounwind {
41+
; CHECK-LABEL: freeze_fsub:
42+
; CHECK: ; %bb.0:
43+
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
44+
; CHECK-NEXT: v_subrev_f32_e32 v0, 1.0, v0
45+
; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1)
46+
; CHECK-NEXT: v_subrev_f32_e32 v0, 1.0, v0
47+
; CHECK-NEXT: s_setpc_b64 s[30:31]
48+
%x = fsub reassoc nsz arcp contract afn float %input, 1.000000e+00
49+
%y = freeze float %x
50+
%z = fsub reassoc nsz arcp contract afn float %y, 1.000000e+00
51+
ret float %z
52+
}
53+
54+
define <4 x float> @freeze_fsub_vec(<4 x float> %input) nounwind {
55+
; CHECK-LABEL: freeze_fsub_vec:
56+
; CHECK: ; %bb.0:
57+
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
58+
; CHECK-NEXT: v_dual_add_f32 v0, 0xc0a00000, v0 :: v_dual_add_f32 v1, 0xc0a00000, v1
59+
; CHECK-NEXT: v_dual_add_f32 v2, 0xc0a00000, v2 :: v_dual_add_f32 v3, 0xc0a00000, v3
60+
; CHECK-NEXT: s_setpc_b64 s[30:31]
61+
%x = fsub reassoc nsz arcp contract afn <4 x float> %input, <float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+00>
62+
%y = freeze <4 x float> %x
63+
%z = fsub reassoc nsz arcp contract afn <4 x float> %y, <float 4.000000e+00, float 3.000000e+00, float 2.000000e+00, float 1.000000e+00>
64+
ret <4 x float> %z
65+
}
66+
67+
define float @freeze_fmul(float %input) nounwind {
68+
; CHECK-LABEL: freeze_fmul:
69+
; CHECK: ; %bb.0:
70+
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
71+
; CHECK-NEXT: v_mul_f32_e32 v0, 4.0, v0
72+
; CHECK-NEXT: s_setpc_b64 s[30:31]
73+
%x = fmul reassoc nsz arcp contract afn float %input, 2.000000e+00
74+
%y = freeze float %x
75+
%z = fmul reassoc nsz arcp contract afn float %y, 2.000000e+00
76+
ret float %z
77+
}
78+
79+
define <8 x float> @freeze_fmul_vec(<8 x float> %input) nounwind {
80+
; CHECK-LABEL: freeze_fmul_vec:
81+
; CHECK: ; %bb.0:
82+
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
83+
; CHECK-NEXT: v_dual_mul_f32 v0, 4.0, v0 :: v_dual_mul_f32 v1, 0x40c00000, v1
84+
; CHECK-NEXT: v_dual_mul_f32 v2, 0x40c00000, v2 :: v_dual_mul_f32 v3, 4.0, v3
85+
; CHECK-NEXT: v_dual_mul_f32 v4, 4.0, v4 :: v_dual_mul_f32 v5, 0x40c00000, v5
86+
; CHECK-NEXT: v_dual_mul_f32 v6, 0x40c00000, v6 :: v_dual_mul_f32 v7, 4.0, v7
87+
; CHECK-NEXT: s_setpc_b64 s[30:31]
88+
%x = fmul reassoc nsz arcp contract afn <8 x float> %input, <float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+00, float 4.000000e+00, float 3.000000e+00, float 2.000000e+00, float 1.000000e+00>
89+
%y = freeze <8 x float> %x
90+
%z = fmul reassoc nsz arcp contract afn <8 x float> %y, <float 4.000000e+00, float 3.000000e+00, float 2.000000e+00, float 1.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+00>
91+
ret <8 x float> %z
92+
}
93+
94+
define float @freeze_fdiv(float %input) nounwind {
95+
; CHECK-LABEL: freeze_fdiv:
96+
; CHECK: ; %bb.0:
97+
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
98+
; CHECK-NEXT: v_mul_f32_e32 v0, 0x3e800000, v0
99+
; CHECK-NEXT: s_setpc_b64 s[30:31]
100+
%x = fdiv reassoc nsz arcp contract afn float %input, 2.000000e+00
101+
%y = freeze float %x
102+
%z = fdiv reassoc nsz arcp contract afn float %y, 2.000000e+00
103+
ret float %z
104+
}
105+
106+
define <8 x float> @freeze_fdiv_vec(<8 x float> %input) nounwind {
107+
; CHECK-LABEL: freeze_fdiv_vec:
108+
; CHECK: ; %bb.0:
109+
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
110+
; CHECK-NEXT: v_dual_mul_f32 v3, 0x3e800000, v3 :: v_dual_mul_f32 v4, 0x3e800000, v4
111+
; CHECK-NEXT: v_dual_mul_f32 v0, 0x3e800000, v0 :: v_dual_mul_f32 v7, 0x3e800000, v7
112+
; CHECK-NEXT: v_dual_mul_f32 v1, 0x3e2aaaab, v1 :: v_dual_mul_f32 v2, 0x3e2aaaab, v2
113+
; CHECK-NEXT: v_dual_mul_f32 v5, 0x3e2aaaab, v5 :: v_dual_mul_f32 v6, 0x3e2aaaab, v6
114+
; CHECK-NEXT: s_setpc_b64 s[30:31]
115+
%x = fdiv reassoc nsz arcp contract afn <8 x float> %input, <float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+00, float 4.000000e+00, float 3.000000e+00, float 2.000000e+00, float 1.000000e+00>
116+
%y = freeze <8 x float> %x
117+
%z = fdiv reassoc nsz arcp contract afn <8 x float> %y, <float 4.000000e+00, float 3.000000e+00, float 2.000000e+00, float 1.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+00>
118+
ret <8 x float> %z
119+
}
120+
121+
define float @freeze_frem(float %input) nounwind {
122+
; CHECK-LABEL: freeze_frem:
123+
; CHECK: ; %bb.0:
124+
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
125+
; CHECK-NEXT: v_mul_f32_e32 v1, 0.5, v0
126+
; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
127+
; CHECK-NEXT: v_trunc_f32_e32 v1, v1
128+
; CHECK-NEXT: v_fmac_f32_e32 v0, -2.0, v1
129+
; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
130+
; CHECK-NEXT: v_mul_f32_e32 v1, 0.5, v0
131+
; CHECK-NEXT: v_trunc_f32_e32 v1, v1
132+
; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1)
133+
; CHECK-NEXT: v_fmac_f32_e32 v0, -2.0, v1
134+
; CHECK-NEXT: s_setpc_b64 s[30:31]
135+
%x = frem reassoc nsz arcp contract afn float %input, 2.000000e+00
136+
%y = freeze float %x
137+
%z = frem reassoc nsz arcp contract afn float %y, 2.000000e+00
138+
ret float %z
139+
}
140+
141+
define <8 x float> @freeze_frem_vec(<8 x float> %input) nounwind {
142+
; CHECK-LABEL: freeze_frem_vec:
143+
; CHECK: ; %bb.0:
144+
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
145+
; CHECK-NEXT: v_dual_mul_f32 v8, 0x3e800000, v4 :: v_dual_mul_f32 v9, 0x3e800000, v3
146+
; CHECK-NEXT: v_trunc_f32_e32 v11, v0
147+
; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
148+
; CHECK-NEXT: v_trunc_f32_e32 v8, v8
149+
; CHECK-NEXT: v_trunc_f32_e32 v9, v9
150+
; CHECK-NEXT: v_mul_f32_e32 v10, 0.5, v6
151+
; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
152+
; CHECK-NEXT: v_dual_sub_f32 v0, v0, v11 :: v_dual_mul_f32 v11, 0x3eaaaaab, v5
153+
; CHECK-NEXT: v_dual_fmac_f32 v4, -4.0, v8 :: v_dual_fmac_f32 v3, -4.0, v9
154+
; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
155+
; CHECK-NEXT: v_trunc_f32_e32 v10, v10
156+
; CHECK-NEXT: v_trunc_f32_e32 v9, v7
157+
; CHECK-NEXT: v_dual_fmac_f32 v6, -2.0, v10 :: v_dual_sub_f32 v7, v7, v9
158+
; CHECK-NEXT: v_mul_f32_e32 v8, 0.5, v1
159+
; CHECK-NEXT: v_trunc_f32_e32 v9, v11
160+
; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
161+
; CHECK-NEXT: v_mul_f32_e32 v11, 0x3e800000, v7
162+
; CHECK-NEXT: v_trunc_f32_e32 v8, v8
163+
; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
164+
; CHECK-NEXT: v_fmac_f32_e32 v1, -2.0, v8
165+
; CHECK-NEXT: v_fmac_f32_e32 v5, 0xc0400000, v9
166+
; CHECK-NEXT: v_mul_f32_e32 v10, 0x3eaaaaab, v2
167+
; CHECK-NEXT: v_mul_f32_e32 v12, 0x3e800000, v0
168+
; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
169+
; CHECK-NEXT: v_trunc_f32_e32 v8, v10
170+
; CHECK-NEXT: v_trunc_f32_e32 v10, v12
171+
; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
172+
; CHECK-NEXT: v_fmac_f32_e32 v2, 0xc0400000, v8
173+
; CHECK-NEXT: v_trunc_f32_e32 v8, v11
174+
; CHECK-NEXT: v_mul_f32_e32 v12, 0x3eaaaaab, v1
175+
; CHECK-NEXT: v_dual_fmac_f32 v0, -4.0, v10 :: v_dual_mul_f32 v11, 0.5, v5
176+
; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
177+
; CHECK-NEXT: v_fmac_f32_e32 v7, -4.0, v8
178+
; CHECK-NEXT: v_trunc_f32_e32 v9, v12
179+
; CHECK-NEXT: v_mul_f32_e32 v12, 0x3eaaaaab, v6
180+
; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
181+
; CHECK-NEXT: v_fmac_f32_e32 v1, 0xc0400000, v9
182+
; CHECK-NEXT: v_trunc_f32_e32 v9, v11
183+
; CHECK-NEXT: v_trunc_f32_e32 v11, v3
184+
; CHECK-NEXT: v_dual_mul_f32 v10, 0.5, v2 :: v_dual_fmac_f32 v5, -2.0, v9
185+
; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
186+
; CHECK-NEXT: v_sub_f32_e32 v3, v3, v11
187+
; CHECK-NEXT: v_trunc_f32_e32 v8, v10
188+
; CHECK-NEXT: v_trunc_f32_e32 v10, v12
189+
; CHECK-NEXT: v_trunc_f32_e32 v12, v4
190+
; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
191+
; CHECK-NEXT: v_fmac_f32_e32 v2, -2.0, v8
192+
; CHECK-NEXT: v_fmac_f32_e32 v6, 0xc0400000, v10
193+
; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_3)
194+
; CHECK-NEXT: v_sub_f32_e32 v4, v4, v12
195+
; CHECK-NEXT: s_setpc_b64 s[30:31]
196+
%x = frem reassoc nsz arcp contract afn <8 x float> %input, <float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+00, float 4.000000e+00, float 3.000000e+00, float 2.000000e+00, float 1.000000e+00>
197+
%y = freeze <8 x float> %x
198+
%z = frem reassoc nsz arcp contract afn <8 x float> %y, <float 4.000000e+00, float 3.000000e+00, float 2.000000e+00, float 1.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+00>
199+
ret <8 x float> %z
200+
}

0 commit comments

Comments
 (0)