[RISCV] Fix incorrect runline for test

Author: preames

llvm/test/CodeGen/RISCV/rvv/stack-slot-coloring.ll

@@ -1,6 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s
-; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefix=RV32
+; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefix=RV64
 
 declare void @foo()
 
@@ -474,5 +474,3 @@ define void @test_m1_then_m2(ptr %p, ptr %p2) {
   store <vscale x 16 x i8> %v2, ptr %p2
   ret void
 }
-;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
-; CHECK: {{.*}}