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[NFC] Fix -WError for unused Encode/Decode ZK methods
Remove the unused functions and register classes from the change below llvm@4679583
1 parent 8417f6a commit 42ba452

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9 files changed

+13
-63
lines changed

9 files changed

+13
-63
lines changed

‎llvm/lib/Target/AArch64/AArch64RegisterInfo.td‎

Lines changed: 0 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -1210,15 +1210,6 @@ def ZPRMul2AsmOp32_Hi : ZPRAsmOperand<"VectorS_Hi", 32, "Mul2_Hi">;
12101210
def ZPRMul2AsmOp64_Lo : ZPRAsmOperand<"VectorD_Lo", 64, "Mul2_Lo">;
12111211
def ZPRMul2AsmOp64_Hi : ZPRAsmOperand<"VectorD_Hi", 64, "Mul2_Hi">;
12121212

1213-
def ZPR_K : RegisterClass<"AArch64", [untyped], 128,
1214-
(add Z20, Z21, Z22, Z23, Z28, Z29, Z30, Z31)>;
1215-
1216-
def ZK : RegisterOperand<ZPR_K, "printSVERegOp<>">{
1217-
let EncoderMethod = "EncodeZK";
1218-
let DecoderMethod = "DecodeZK";
1219-
let ParserMatchClass = ZPRAsmOperand<"Vector_20to23or28to31", 0, "_K">;
1220-
}
1221-
12221213
def ZPR8Mul2_Lo : ZPRMul2_MinToMaxRegOp<"b", ZPRMul2AsmOp8_Lo, 0, 14, ElementSizeB, ZPRMul2_Lo>;
12231214
def ZPR8Mul2_Hi : ZPRMul2_MinToMaxRegOp<"b", ZPRMul2AsmOp8_Hi, 16, 30, ElementSizeB, ZPRMul2_Hi>;
12241215
def ZPR16Mul2_Lo : ZPRMul2_MinToMaxRegOp<"h", ZPRMul2AsmOp16_Lo, 0, 14, ElementSizeH, ZPRMul2_Lo>;

‎llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp‎

Lines changed: 0 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1264,7 +1264,6 @@ class AArch64Operand : public MCParsedAsmOperand {
12641264
case AArch64::ZPR_4bRegClassID:
12651265
case AArch64::ZPRMul2_LoRegClassID:
12661266
case AArch64::ZPRMul2_HiRegClassID:
1267-
case AArch64::ZPR_KRegClassID:
12681267
RK = RegKind::SVEDataVector;
12691268
break;
12701269
case AArch64::PPRRegClassID:
@@ -6119,9 +6118,6 @@ bool AArch64AsmParser::showMatchError(SMLoc Loc, unsigned ErrCode,
61196118
case Match_InvalidZPRMul2_Hi64:
61206119
return Error(Loc, "Invalid restricted vector register, expected even "
61216120
"register in z16.d..z30.d");
6122-
case Match_InvalidZPR_K0:
6123-
return Error(Loc, "invalid restricted vector register, expected register "
6124-
"in z20..z23 or z28..z31");
61256121
case Match_InvalidSVEPattern:
61266122
return Error(Loc, "invalid predicate pattern");
61276123
case Match_InvalidSVEPPRorPNRAnyReg:
@@ -6831,7 +6827,6 @@ bool AArch64AsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
68316827
case Match_InvalidZPRMul2_Hi32:
68326828
case Match_InvalidZPRMul2_Lo64:
68336829
case Match_InvalidZPRMul2_Hi64:
6834-
case Match_InvalidZPR_K0:
68356830
case Match_InvalidSVEVectorList2x8Mul2:
68366831
case Match_InvalidSVEVectorList2x16Mul2:
68376832
case Match_InvalidSVEVectorList2x32Mul2:

‎llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp‎

Lines changed: 0 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -49,8 +49,6 @@ template <unsigned Min, unsigned Max>
4949
static DecodeStatus DecodeZPRMul2_MinMax(MCInst &Inst, unsigned RegNo,
5050
uint64_t Address,
5151
const MCDisassembler *Decoder);
52-
static DecodeStatus DecodeZK(MCInst &Inst, unsigned RegNo, uint64_t Address,
53-
const MCDisassembler *Decoder);
5452
template <unsigned Min, unsigned Max>
5553
static DecodeStatus DecodeZPR2Mul2RegisterClass(MCInst &Inst, unsigned RegNo,
5654
uint64_t Address,
@@ -389,22 +387,6 @@ static DecodeStatus DecodeZPR2Mul2RegisterClass(MCInst &Inst, unsigned RegNo,
389387
return Success;
390388
}
391389

392-
// Zk Is the name of the control vector register Z20-Z23 or Z28-Z31, encoded in
393-
// the "K:Zk" fields. Z20-Z23 = 000, 001,010, 011 and Z28-Z31 = 100, 101, 110,
394-
// 111
395-
static DecodeStatus DecodeZK(MCInst &Inst, unsigned RegNo, uint64_t Address,
396-
const MCDisassembler *Decoder) {
397-
// RegNo < 4 => Reg is in Z20-Z23 (offset 20)
398-
// RegNo >= 4 => Reg is in Z28-Z31 (offset 24)
399-
unsigned Reg = (RegNo < 4) ? (RegNo + 20) : (RegNo + 24);
400-
if (!(Reg >= 20 && Reg <= 23) && !(Reg >= 28 && Reg <= 31))
401-
return Fail;
402-
unsigned Register =
403-
AArch64MCRegisterClasses[AArch64::ZPRRegClassID].getRegister(Reg);
404-
Inst.addOperand(MCOperand::createReg(Register));
405-
return Success;
406-
}
407-
408390
static DecodeStatus DecodeZPR4Mul4RegisterClass(MCInst &Inst, unsigned RegNo,
409391
uint64_t Address,
410392
const void *Decoder) {

‎llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp‎

Lines changed: 0 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -195,9 +195,6 @@ class AArch64MCCodeEmitter : public MCCodeEmitter {
195195
uint32_t EncodeRegMul_MinMax(const MCInst &MI, unsigned OpIdx,
196196
SmallVectorImpl<MCFixup> &Fixups,
197197
const MCSubtargetInfo &STI) const;
198-
uint32_t EncodeZK(const MCInst &MI, unsigned OpIdx,
199-
SmallVectorImpl<MCFixup> &Fixups,
200-
const MCSubtargetInfo &STI) const;
201198
uint32_t EncodePNR_p8to15(const MCInst &MI, unsigned OpIdx,
202199
SmallVectorImpl<MCFixup> &Fixups,
203200
const MCSubtargetInfo &STI) const;
@@ -576,21 +573,6 @@ AArch64MCCodeEmitter::EncodeRegMul_MinMax(const MCInst &MI, unsigned OpIdx,
576573
return (RegVal - Min) / Multiple;
577574
}
578575

579-
// Zk Is the name of the control vector register Z20-Z23 or Z28-Z31, encoded in
580-
// the "K:Zk" fields. Z20-Z23 = 000, 001,010, 011 and Z28-Z31 = 100, 101, 110,
581-
// 111
582-
uint32_t AArch64MCCodeEmitter::EncodeZK(const MCInst &MI, unsigned OpIdx,
583-
SmallVectorImpl<MCFixup> &Fixups,
584-
const MCSubtargetInfo &STI) const {
585-
auto RegOpnd = MI.getOperand(OpIdx).getReg();
586-
unsigned RegVal = Ctx.getRegisterInfo()->getEncodingValue(RegOpnd);
587-
// Z28 => RegVal = 28 (28 - 24 = 4) Z28 = 4
588-
if (RegOpnd > AArch64::Z27)
589-
return (RegVal - 24);
590-
// Z20 => RegVal = 20 (20 -20 = 0) Z20 = 0
591-
return (RegVal - 20);
592-
}
593-
594576
uint32_t
595577
AArch64MCCodeEmitter::EncodePNR_p8to15(const MCInst &MI, unsigned OpIdx,
596578
SmallVectorImpl<MCFixup> &Fixups,

‎llvm/test/CodeGen/AArch64/GlobalISel/regbank-inlineasm.mir‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -57,7 +57,7 @@ tracksRegLiveness: true
5757
body: |
5858
bb.1:
5959
; CHECK-LABEL: name: inlineasm_virt_reg_output
60-
; CHECK: INLINEASM &"mov ${0:w}, 7", 0 /* attdialect */, 2490378 /* regdef:GPR32common */, def %0
60+
; CHECK: INLINEASM &"mov ${0:w}, 7", 0 /* attdialect */, 2490378 /* regdef:FPR32_with_hsub_in_FPR16_lo */, def %0
6161
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr(s32) = COPY %0
6262
; CHECK-NEXT: $w0 = COPY [[COPY]](s32)
6363
; CHECK-NEXT: RET_ReallyLR implicit $w0
@@ -75,7 +75,7 @@ tracksRegLiveness: true
7575
body: |
7676
bb.1:
7777
; CHECK-LABEL: name: inlineasm_virt_mixed_types
78-
; CHECK: INLINEASM &"mov $0, #0; mov $1, #0", 0 /* attdialect */, 2490378 /* regdef:GPR32common */, def %0, 3342346 /* regdef:FPR64 */, def %1
78+
; CHECK: INLINEASM &"mov $0, #0; mov $1, #0", 0 /* attdialect */, 2490378 /* regdef:FPR32_with_hsub_in_FPR16_lo */, def %0, 3342346 /* regdef:GPR64 */, def %1
7979
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr(s32) = COPY %0
8080
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr(s64) = COPY %1
8181
; CHECK-NEXT: $d0 = COPY [[COPY1]](s64)

‎llvm/test/CodeGen/AArch64/aarch64-sve-asm.ll‎

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -13,7 +13,7 @@ define <vscale x 16 x i8> @test_svadd_i8(<vscale x 16 x i8> %Zn, <vscale x 16 x
1313
; CHECK-NEXT: [[COPY1:%[0-9]+]]:zpr = COPY $z0
1414
; CHECK-NEXT: [[COPY2:%[0-9]+]]:zpr = COPY [[COPY1]]
1515
; CHECK-NEXT: [[COPY3:%[0-9]+]]:zpr_3b = COPY [[COPY]]
16-
; CHECK-NEXT: INLINEASM &"add $0.b, $1.b, $2.b", 0 /* attdialect */, 5767178 /* regdef:ZPR */, def %2, 5767177 /* reguse:ZPR */, [[COPY2]], 6357001 /* reguse:ZPR_3b */, [[COPY3]]
16+
; CHECK-NEXT: INLINEASM &"add $0.b, $1.b, $2.b", 0 /* attdialect */, 5701642 /* regdef:ZPR */, def %2, 5701641 /* reguse:ZPR */, [[COPY2]], 6291465 /* reguse:ZPR_3b */, [[COPY3]]
1717
; CHECK-NEXT: $z0 = COPY %2
1818
; CHECK-NEXT: RET_ReallyLR implicit $z0
1919
%1 = tail call <vscale x 16 x i8> asm "add $0.b, $1.b, $2.b", "=w,w,y"(<vscale x 16 x i8> %Zn, <vscale x 16 x i8> %Zm)
@@ -29,7 +29,7 @@ define <vscale x 2 x i64> @test_svsub_i64(<vscale x 2 x i64> %Zn, <vscale x 2 x
2929
; CHECK-NEXT: [[COPY1:%[0-9]+]]:zpr = COPY $z0
3030
; CHECK-NEXT: [[COPY2:%[0-9]+]]:zpr = COPY [[COPY1]]
3131
; CHECK-NEXT: [[COPY3:%[0-9]+]]:zpr_4b = COPY [[COPY]]
32-
; CHECK-NEXT: INLINEASM &"sub $0.d, $1.d, $2.d", 0 /* attdialect */, 5767178 /* regdef:ZPR */, def %2, 5767177 /* reguse:ZPR */, [[COPY2]], 6029321 /* reguse:ZPR_4b */, [[COPY3]]
32+
; CHECK-NEXT: INLINEASM &"sub $0.d, $1.d, $2.d", 0 /* attdialect */, 5701642 /* regdef:ZPR */, def %2, 5701641 /* reguse:ZPR */, [[COPY2]], 5963785 /* reguse:ZPR_4b */, [[COPY3]]
3333
; CHECK-NEXT: $z0 = COPY %2
3434
; CHECK-NEXT: RET_ReallyLR implicit $z0
3535
%1 = tail call <vscale x 2 x i64> asm "sub $0.d, $1.d, $2.d", "=w,w,x"(<vscale x 2 x i64> %Zn, <vscale x 2 x i64> %Zm)
@@ -45,7 +45,7 @@ define <vscale x 8 x half> @test_svfmul_f16(<vscale x 8 x half> %Zn, <vscale x 8
4545
; CHECK-NEXT: [[COPY1:%[0-9]+]]:zpr = COPY $z0
4646
; CHECK-NEXT: [[COPY2:%[0-9]+]]:zpr = COPY [[COPY1]]
4747
; CHECK-NEXT: [[COPY3:%[0-9]+]]:zpr_3b = COPY [[COPY]]
48-
; CHECK-NEXT: INLINEASM &"fmul $0.h, $1.h, $2.h", 0 /* attdialect */, 5767178 /* regdef:ZPR */, def %2, 5767177 /* reguse:ZPR */, [[COPY2]], 6357001 /* reguse:ZPR_3b */, [[COPY3]]
48+
; CHECK-NEXT: INLINEASM &"fmul $0.h, $1.h, $2.h", 0 /* attdialect */, 5701642 /* regdef:ZPR */, def %2, 5701641 /* reguse:ZPR */, [[COPY2]], 6291465 /* reguse:ZPR_3b */, [[COPY3]]
4949
; CHECK-NEXT: $z0 = COPY %2
5050
; CHECK-NEXT: RET_ReallyLR implicit $z0
5151
%1 = tail call <vscale x 8 x half> asm "fmul $0.h, $1.h, $2.h", "=w,w,y"(<vscale x 8 x half> %Zn, <vscale x 8 x half> %Zm)
@@ -61,7 +61,7 @@ define <vscale x 4 x float> @test_svfmul_f(<vscale x 4 x float> %Zn, <vscale x 4
6161
; CHECK-NEXT: [[COPY1:%[0-9]+]]:zpr = COPY $z0
6262
; CHECK-NEXT: [[COPY2:%[0-9]+]]:zpr = COPY [[COPY1]]
6363
; CHECK-NEXT: [[COPY3:%[0-9]+]]:zpr_4b = COPY [[COPY]]
64-
; CHECK-NEXT: INLINEASM &"fmul $0.s, $1.s, $2.s", 0 /* attdialect */, 5767178 /* regdef:ZPR */, def %2, 5767177 /* reguse:ZPR */, [[COPY2]], 6029321 /* reguse:ZPR_4b */, [[COPY3]]
64+
; CHECK-NEXT: INLINEASM &"fmul $0.s, $1.s, $2.s", 0 /* attdialect */, 5701642 /* regdef:ZPR */, def %2, 5701641 /* reguse:ZPR */, [[COPY2]], 5963785 /* reguse:ZPR_4b */, [[COPY3]]
6565
; CHECK-NEXT: $z0 = COPY %2
6666
; CHECK-NEXT: RET_ReallyLR implicit $z0
6767
%1 = tail call <vscale x 4 x float> asm "fmul $0.s, $1.s, $2.s", "=w,w,x"(<vscale x 4 x float> %Zn, <vscale x 4 x float> %Zm)
@@ -79,7 +79,7 @@ define <vscale x 8 x half> @test_svfadd_f16(<vscale x 16 x i1> %Pg, <vscale x 8
7979
; CHECK-NEXT: [[COPY3:%[0-9]+]]:ppr_3b = COPY [[COPY2]]
8080
; CHECK-NEXT: [[COPY4:%[0-9]+]]:zpr = COPY [[COPY1]]
8181
; CHECK-NEXT: [[COPY5:%[0-9]+]]:zpr = COPY [[COPY]]
82-
; CHECK-NEXT: INLINEASM &"fadd $0.h, $1/m, $2.h, $3.h", 0 /* attdialect */, 5767178 /* regdef:ZPR */, def %3, 720905 /* reguse:PPR_3b */, [[COPY3]], 5767177 /* reguse:ZPR */, [[COPY4]], 5767177 /* reguse:ZPR */, [[COPY5]]
82+
; CHECK-NEXT: INLINEASM &"fadd $0.h, $1/m, $2.h, $3.h", 0 /* attdialect */, 5701642 /* regdef:ZPR */, def %3, 655369 /* reguse:PPR_3b */, [[COPY3]], 5701641 /* reguse:ZPR */, [[COPY4]], 5701641 /* reguse:ZPR */, [[COPY5]]
8383
; CHECK-NEXT: $z0 = COPY %3
8484
; CHECK-NEXT: RET_ReallyLR implicit $z0
8585
%1 = tail call <vscale x 8 x half> asm "fadd $0.h, $1/m, $2.h, $3.h", "=w,@3Upl,w,w"(<vscale x 16 x i1> %Pg, <vscale x 8 x half> %Zn, <vscale x 8 x half> %Zm)
@@ -95,7 +95,7 @@ define <vscale x 4 x i32> @test_incp(<vscale x 16 x i1> %Pg, <vscale x 4 x i32>
9595
; CHECK-NEXT: [[COPY1:%[0-9]+]]:ppr = COPY $p0
9696
; CHECK-NEXT: [[COPY2:%[0-9]+]]:ppr = COPY [[COPY1]]
9797
; CHECK-NEXT: [[COPY3:%[0-9]+]]:zpr = COPY [[COPY]]
98-
; CHECK-NEXT: INLINEASM &"incp $0.s, $1", 0 /* attdialect */, 5767178 /* regdef:ZPR */, def %2, 458761 /* reguse:PPR */, [[COPY2]], 2147483657 /* reguse tiedto:$0 */, [[COPY3]](tied-def 3)
98+
; CHECK-NEXT: INLINEASM &"incp $0.s, $1", 0 /* attdialect */, 5701642 /* regdef:ZPR */, def %2, 393225 /* reguse:PPR */, [[COPY2]], 2147483657 /* reguse tiedto:$0 */, [[COPY3]](tied-def 3)
9999
; CHECK-NEXT: $z0 = COPY %2
100100
; CHECK-NEXT: RET_ReallyLR implicit $z0
101101
%1 = tail call <vscale x 4 x i32> asm "incp $0.s, $1", "=w,@3Upa,0"(<vscale x 16 x i1> %Pg, <vscale x 4 x i32> %Zn)
@@ -113,7 +113,7 @@ define <vscale x 8 x half> @test_svfadd_f16_Uph_constraint(<vscale x 16 x i1> %P
113113
; CHECK-NEXT: [[COPY3:%[0-9]+]]:ppr_p8to15 = COPY [[COPY2]]
114114
; CHECK-NEXT: [[COPY4:%[0-9]+]]:zpr = COPY [[COPY1]]
115115
; CHECK-NEXT: [[COPY5:%[0-9]+]]:zpr = COPY [[COPY]]
116-
; CHECK-NEXT: INLINEASM &"fadd $0.h, $1/m, $2.h, $3.h", 0 /* attdialect */, 5767178 /* regdef:ZPR */, def %3, 786441 /* reguse:PPR_p8to15 */, [[COPY3]], 5767177 /* reguse:ZPR */, [[COPY4]], 5767177 /* reguse:ZPR */, [[COPY5]]
116+
; CHECK-NEXT: INLINEASM &"fadd $0.h, $1/m, $2.h, $3.h", 0 /* attdialect */, 5701642 /* regdef:ZPR */, def %3, 720905 /* reguse:PPR_p8to15 */, [[COPY3]], 5701641 /* reguse:ZPR */, [[COPY4]], 5701641 /* reguse:ZPR */, [[COPY5]]
117117
; CHECK-NEXT: $z0 = COPY %3
118118
; CHECK-NEXT: RET_ReallyLR implicit $z0
119119
%1 = tail call <vscale x 8 x half> asm "fadd $0.h, $1/m, $2.h, $3.h", "=w,@3Uph,w,w"(<vscale x 16 x i1> %Pg, <vscale x 8 x half> %Zn, <vscale x 8 x half> %Zm)

‎llvm/test/CodeGen/AArch64/emit_fneg_with_non_register_operand.mir‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -91,10 +91,10 @@ body: |
9191
; CHECK-NEXT: {{ $}}
9292
; CHECK-NEXT: [[LOADgot:%[0-9]+]]:gpr64common = LOADgot target-flags(aarch64-got) @c
9393
; CHECK-NEXT: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[LOADgot]], 0 :: (dereferenceable load (s64) from @c)
94-
; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, 3342346 /* regdef:FPR64 */, def %2, 2147483657 /* reguse tiedto:$0 */, [[LDRDui]](tied-def 3)
94+
; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, 3342346 /* regdef:GPR64 */, def %2, 2147483657 /* reguse tiedto:$0 */, [[LDRDui]](tied-def 3)
9595
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY %2
9696
; CHECK-NEXT: [[LDRDui1:%[0-9]+]]:fpr64 = LDRDui [[LOADgot]], 0 :: (dereferenceable load (s64) from @c)
97-
; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, 3342346 /* regdef:FPR64 */, def %4, 2147483657 /* reguse tiedto:$0 */, [[LDRDui1]](tied-def 3)
97+
; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, 3342346 /* regdef:GPR64 */, def %4, 2147483657 /* reguse tiedto:$0 */, [[LDRDui1]](tied-def 3)
9898
; CHECK-NEXT: [[FNEGDr:%[0-9]+]]:fpr64 = FNEGDr %2
9999
; CHECK-NEXT: nofpexcept FCMPDrr %4, killed [[FNEGDr]], implicit-def $nzcv, implicit $fpcr
100100
; CHECK-NEXT: Bcc 1, %bb.2, implicit $nzcv

‎llvm/test/CodeGen/AArch64/fmlal-loreg.ll‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -11,8 +11,8 @@ define <4 x float> @test(ptr %lhs_panel, ptr %rhs_panel, <4 x float> %a) {
1111
; CHECK-NEXT: .cfi_def_cfa_offset 16
1212
; CHECK-NEXT: .cfi_offset b8, -16
1313
; CHECK-NEXT: fmov x8, d0
14-
; CHECK-NEXT: ldr q16, [x1]
1514
; CHECK-NEXT: ldr q8, [x0]
15+
; CHECK-NEXT: ldr q16, [x1]
1616
; CHECK-NEXT: lsr x9, x8, #32
1717
; CHECK-NEXT: //APP
1818
; CHECK-NEXT: nop

‎llvm/test/CodeGen/AArch64/peephole-insvigpr.mir‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -487,7 +487,7 @@ body: |
487487
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x0
488488
; CHECK-NEXT: [[DEF:%[0-9]+]]:gpr64all = IMPLICIT_DEF
489489
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64sp = COPY [[DEF]]
490-
; CHECK-NEXT: INLINEASM &"ldr ${0:s}, $1", 8 /* mayload attdialect */, 3342346 /* regdef:FPR64 */, def %1, 262158 /* mem:m */, killed [[COPY1]]
490+
; CHECK-NEXT: INLINEASM &"ldr ${0:s}, $1", 8 /* mayload attdialect */, 3342346 /* regdef:GPR64 */, def %1, 262158 /* mem:m */, killed [[COPY1]]
491491
; CHECK-NEXT: [[MOVIv2d_ns:%[0-9]+]]:fpr128 = MOVIv2d_ns 0
492492
; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY [[MOVIv2d_ns]].dsub
493493
; CHECK-NEXT: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF

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