[LLVM][TableGen] Change CodeGenTarget to use const RecordKeeper (llvm#108752)

Change CodeGenTarget to use const RecordKeeper.

This is a part of effort to have better const correctness in TableGen
backends:


https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089

Author: jurahul

llvm/utils/TableGen/AsmWriterEmitter.cpp

@@ -636,7 +636,7 @@ void AsmWriterEmitter::EmitGetRegisterName(raw_ostream &O) {
   Record *AsmWriter = Target.getAsmWriter();
   StringRef ClassName = AsmWriter->getValueAsString("AsmWriterClassName");
   const auto &Registers = Target.getRegBank().getRegisters();
-  const std::vector<Record *> &AltNameIndices = Target.getRegAltNameIndices();
+  ArrayRef<const Record *> AltNameIndices = Target.getRegAltNameIndices();
   bool hasAltNames = AltNameIndices.size() > 1;
   StringRef Namespace = Registers.front().TheDef->getValueAsString("Namespace");
 

llvm/utils/TableGen/Common/CodeGenTarget.cpp

@@ -85,9 +85,9 @@ std::string llvm::getQualifiedName(const Record *R) {
 
 /// getTarget - Return the current instance of the Target class.
 ///
-CodeGenTarget::CodeGenTarget(RecordKeeper &records)
+CodeGenTarget::CodeGenTarget(const RecordKeeper &records)
     : Records(records), CGH(records), Intrinsics(records) {
-  std::vector<Record *> Targets = Records.getAllDerivedDefinitions("Target");
+  ArrayRef<const Record *> Targets = Records.getAllDerivedDefinitions("Target");
   if (Targets.size() == 0)
     PrintFatalError("No 'Target' subclasses defined!");
   if (Targets.size() != 1)
@@ -223,11 +223,6 @@ std::optional<CodeGenRegisterClass *> CodeGenTarget::getSuperRegForSubReg(
   return Candidates[0];
 }
 
-void CodeGenTarget::ReadRegAltNameIndices() const {
-  RegAltNameIndices = Records.getAllDerivedDefinitions("RegAltNameIndex");
-  llvm::sort(RegAltNameIndices, LessRecord());
-}
-
 /// getRegisterByName - If there is a register with the specific AsmName,
 /// return it.
 const CodeGenRegister *CodeGenTarget::getRegisterByName(StringRef Name) const {
@@ -271,12 +266,13 @@ CodeGenSchedModels &CodeGenTarget::getSchedModels() const {
 }
 
 void CodeGenTarget::ReadInstructions() const {
-  std::vector<Record *> Insts = Records.getAllDerivedDefinitions("Instruction");
+  ArrayRef<const Record *> Insts =
+      Records.getAllDerivedDefinitions("Instruction");
   if (Insts.size() <= 2)
     PrintFatalError("No 'Instruction' subclasses defined!");
 
   // Parse the instructions defined in the .td file.
-  for (Record *R : Insts) {
+  for (const Record *R : Insts) {
     Instructions[R] = std::make_unique<CodeGenInstruction>(R);
     if (Instructions[R]->isVariableLengthEncoding())
       HasVariableLengthEncodings = true;
@@ -286,7 +282,7 @@ void CodeGenTarget::ReadInstructions() const {
 static const CodeGenInstruction *GetInstByName(
     const char *Name,
     const DenseMap<const Record *, std::unique_ptr<CodeGenInstruction>> &Insts,
-    RecordKeeper &Records) {
+    const RecordKeeper &Records) {
   const Record *Rec = Records.getDef(Name);
 
   const auto I = Insts.find(Rec);
@@ -358,9 +354,8 @@ void CodeGenTarget::reverseBitsForLittleEndianEncoding() {
   if (!isLittleEndianEncoding())
     return;
 
-  std::vector<Record *> Insts =
-      Records.getAllDerivedDefinitions("InstructionEncoding");
-  for (Record *R : Insts) {
+  for (const Record *R :
+       Records.getAllDerivedDefinitions("InstructionEncoding")) {
     if (R->getValueAsString("Namespace") == "TargetOpcode" ||
         R->getValueAsBit("isPseudo"))
       continue;
@@ -383,11 +378,15 @@ void CodeGenTarget::reverseBitsForLittleEndianEncoding() {
       NewBits[middle] = BI->getBit(middle);
     }
 
-    BitsInit *NewBI = BitsInit::get(Records, NewBits);
+    RecordKeeper &MutableRC = const_cast<RecordKeeper &>(Records);
+    BitsInit *NewBI = BitsInit::get(MutableRC, NewBits);
 
-    // Update the bits in reversed order so that emitInstrOpBits will get the
-    // correct endianness.
-    R->getValue("Inst")->setValue(NewBI);
+    // Update the bits in reversed order so that emitters will get the correct
+    // endianness.
+    // FIXME: Eliminate mutation of TG records by creating a helper function
+    // to reverse bits and maintain a cache instead of mutating records.
+    Record *MutableR = const_cast<Record *>(R);
+    MutableR->getValue("Inst")->setValue(NewBI);
   }
 }
 

llvm/utils/TableGen/Common/CodeGenTarget.h

@@ -56,19 +56,18 @@ std::string getQualifiedName(const Record *R);
 /// CodeGenTarget - This class corresponds to the Target class in the .td files.
 ///
 class CodeGenTarget {
-  RecordKeeper &Records;
-  Record *TargetRec;
+  const RecordKeeper &Records;
+  const Record *TargetRec;
 
   mutable DenseMap<const Record *, std::unique_ptr<CodeGenInstruction>>
       Instructions;
   mutable std::unique_ptr<CodeGenRegBank> RegBank;
-  mutable std::vector<Record *> RegAltNameIndices;
+  mutable ArrayRef<const Record *> RegAltNameIndices;
   mutable SmallVector<ValueTypeByHwMode, 8> LegalValueTypes;
   CodeGenHwModes CGH;
-  std::vector<Record *> MacroFusions;
+  ArrayRef<const Record *> MacroFusions;
   mutable bool HasVariableLengthEncodings = false;
 
-  void ReadRegAltNameIndices() const;
   void ReadInstructions() const;
   void ReadLegalValueTypes() const;
 
@@ -81,10 +80,10 @@ class CodeGenTarget {
   mutable unsigned NumPseudoInstructions = 0;
 
 public:
-  CodeGenTarget(RecordKeeper &Records);
+  CodeGenTarget(const RecordKeeper &Records);
   ~CodeGenTarget();
 
-  Record *getTargetRecord() const { return TargetRec; }
+  const Record *getTargetRecord() const { return TargetRec; }
   StringRef getName() const;
 
   /// getInstNamespace - Return the target-specific instruction namespace.
@@ -135,9 +134,9 @@ class CodeGenTarget {
   /// return it.
   const CodeGenRegister *getRegisterByName(StringRef Name) const;
 
-  const std::vector<Record *> &getRegAltNameIndices() const {
+  ArrayRef<const Record *> getRegAltNameIndices() const {
     if (RegAltNameIndices.empty())
-      ReadRegAltNameIndices();
+      RegAltNameIndices = Records.getAllDerivedDefinitions("RegAltNameIndex");
     return RegAltNameIndices;
   }
 
@@ -159,7 +158,7 @@ class CodeGenTarget {
 
   bool hasMacroFusion() const { return !MacroFusions.empty(); }
 
-  const std::vector<Record *> getMacroFusions() const { return MacroFusions; }
+  ArrayRef<const Record *> getMacroFusions() const { return MacroFusions; }
 
 private:
   DenseMap<const Record *, std::unique_ptr<CodeGenInstruction>> &

llvm/utils/TableGen/RegisterInfoEmitter.cpp

@@ -152,8 +152,7 @@ void RegisterInfoEmitter::runEnums(raw_ostream &OS, CodeGenTarget &Target,
       OS << "} // end namespace " << Namespace << "\n\n";
   }
 
-  const std::vector<Record *> &RegAltNameIndices =
-      Target.getRegAltNameIndices();
+  ArrayRef<const Record *> RegAltNameIndices = Target.getRegAltNameIndices();
   // If the only definition is the default NoRegAltName, we don't need to
   // emit anything.
   if (RegAltNameIndices.size() > 1) {