Skip to content

Commit 456ca91

Browse files
chaitanyavchaitanyav
authored
[Clang] VectorExprEvaluator::VisitCallExpr / InterpretBuiltin - Allow AVX512 VPSHUFBITQMB intrinsics to be used in constexpr (llvm#168100)
Resolves llvm#161337
1 parent 1264620 commit 456ca91

File tree

7 files changed

+171
-42
lines changed

7 files changed

+171
-42
lines changed

‎clang/include/clang/Basic/BuiltinsX86.td‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1366,15 +1366,15 @@ let Features = "avx512cd", Attributes = [NoThrow, Const, Constexpr, RequiredVect
13661366
def vpconflictsi_512 : X86Builtin<"_Vector<16, int>(_Vector<16, int>)">;
13671367
}
13681368

1369-
let Features = "avx512vl,avx512bitalg", Attributes = [NoThrow, Const, RequiredVectorWidth<128>] in {
1369+
let Features = "avx512vl,avx512bitalg", Attributes = [NoThrow, Const, Constexpr, RequiredVectorWidth<128>] in {
13701370
def vpshufbitqmb128_mask : X86Builtin<"unsigned short(_Vector<16, char>, _Vector<16, char>, unsigned short)">;
13711371
}
13721372

1373-
let Features = "avx512vl,avx512bitalg", Attributes = [NoThrow, Const, RequiredVectorWidth<256>] in {
1373+
let Features = "avx512vl,avx512bitalg", Attributes = [NoThrow, Const, Constexpr, RequiredVectorWidth<256>] in {
13741374
def vpshufbitqmb256_mask : X86Builtin<"unsigned int(_Vector<32, char>, _Vector<32, char>, unsigned int)">;
13751375
}
13761376

1377-
let Features = "avx512bitalg", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in {
1377+
let Features = "avx512bitalg", Attributes = [NoThrow, Const, Constexpr, RequiredVectorWidth<512>] in {
13781378
def vpshufbitqmb512_mask : X86Builtin<"unsigned long long int(_Vector<64, char>, _Vector<64, char>, unsigned long long int)">;
13791379
}
13801380

‎clang/lib/AST/ByteCode/InterpBuiltin.cpp‎

Lines changed: 69 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3468,6 +3468,69 @@ static bool interp__builtin_ia32_shuffle_generic(
34683468
return true;
34693469
}
34703470

3471+
static bool interp__builtin_ia32_shufbitqmb_mask(InterpState &S, CodePtr OpPC,
3472+
const CallExpr *Call) {
3473+
3474+
assert(Call->getNumArgs() == 3);
3475+
3476+
QualType SourceType = Call->getArg(0)->getType();
3477+
QualType ShuffleMaskType = Call->getArg(1)->getType();
3478+
QualType ZeroMaskType = Call->getArg(2)->getType();
3479+
if (!SourceType->isVectorType() || !ShuffleMaskType->isVectorType() ||
3480+
!ZeroMaskType->isIntegerType()) {
3481+
return false;
3482+
}
3483+
3484+
Pointer Source, ShuffleMask;
3485+
APSInt ZeroMask = popToAPSInt(S, Call->getArg(2));
3486+
ShuffleMask = S.Stk.pop<Pointer>();
3487+
Source = S.Stk.pop<Pointer>();
3488+
3489+
const auto *SourceVecT = SourceType->castAs<VectorType>();
3490+
const auto *ShuffleMaskVecT = ShuffleMaskType->castAs<VectorType>();
3491+
assert(SourceVecT->getNumElements() == ShuffleMaskVecT->getNumElements());
3492+
assert(ZeroMask.getBitWidth() == SourceVecT->getNumElements());
3493+
3494+
PrimType SourceElemT = *S.getContext().classify(SourceVecT->getElementType());
3495+
PrimType ShuffleMaskElemT =
3496+
*S.getContext().classify(ShuffleMaskVecT->getElementType());
3497+
3498+
unsigned NumBytesInQWord = 8;
3499+
unsigned NumBitsInByte = 8;
3500+
unsigned NumBytes = SourceVecT->getNumElements();
3501+
unsigned NumQWords = NumBytes / NumBytesInQWord;
3502+
unsigned RetWidth = ZeroMask.getBitWidth();
3503+
APSInt RetMask(llvm::APInt(RetWidth, 0), /*isUnsigned=*/true);
3504+
3505+
for (unsigned QWordId = 0; QWordId != NumQWords; ++QWordId) {
3506+
APInt SourceQWord(64, 0);
3507+
for (unsigned ByteIdx = 0; ByteIdx != NumBytesInQWord; ++ByteIdx) {
3508+
uint64_t Byte = 0;
3509+
INT_TYPE_SWITCH(SourceElemT, {
3510+
Byte = static_cast<uint64_t>(
3511+
Source.elem<T>(QWordId * NumBytesInQWord + ByteIdx));
3512+
});
3513+
SourceQWord.insertBits(APInt(8, Byte & 0xFF), ByteIdx * NumBitsInByte);
3514+
}
3515+
3516+
for (unsigned ByteIdx = 0; ByteIdx != NumBytesInQWord; ++ByteIdx) {
3517+
unsigned SelIdx = QWordId * NumBytesInQWord + ByteIdx;
3518+
unsigned M = 0;
3519+
INT_TYPE_SWITCH(ShuffleMaskElemT, {
3520+
M = static_cast<unsigned>(ShuffleMask.elem<T>(SelIdx)) & 0x3F;
3521+
});
3522+
3523+
if (ZeroMask[SelIdx]) {
3524+
RetMask.setBitVal(SelIdx, SourceQWord[M]);
3525+
}
3526+
}
3527+
}
3528+
3529+
pushInteger(S, RetMask, Call->getType());
3530+
3531+
return true;
3532+
}
3533+
34713534
bool InterpretBuiltin(InterpState &S, CodePtr OpPC, const CallExpr *Call,
34723535
uint32_t BuiltinID) {
34733536
if (!S.getASTContext().BuiltinInfo.isConstantEvaluated(BuiltinID))
@@ -4868,6 +4931,12 @@ bool InterpretBuiltin(InterpState &S, CodePtr OpPC, const CallExpr *Call,
48684931
case X86::BI__builtin_ia32_ucmpq512_mask:
48694932
return interp__builtin_ia32_cmp_mask(S, OpPC, Call, BuiltinID,
48704933
/*IsUnsigned=*/true);
4934+
4935+
case X86::BI__builtin_ia32_vpshufbitqmb128_mask:
4936+
case X86::BI__builtin_ia32_vpshufbitqmb256_mask:
4937+
case X86::BI__builtin_ia32_vpshufbitqmb512_mask:
4938+
return interp__builtin_ia32_shufbitqmb_mask(S, OpPC, Call);
4939+
48714940
case X86::BI__builtin_ia32_pslldqi128_byteshift:
48724941
case X86::BI__builtin_ia32_pslldqi256_byteshift:
48734942
case X86::BI__builtin_ia32_pslldqi512_byteshift:

‎clang/lib/AST/ExprConstant.cpp‎

Lines changed: 42 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -16762,6 +16762,48 @@ bool IntExprEvaluator::VisitBuiltinCallExpr(const CallExpr *E,
1676216762

1676316763
return Success(APValue(RetMask), E);
1676416764
}
16765+
case X86::BI__builtin_ia32_vpshufbitqmb128_mask:
16766+
case X86::BI__builtin_ia32_vpshufbitqmb256_mask:
16767+
case X86::BI__builtin_ia32_vpshufbitqmb512_mask: {
16768+
assert(E->getNumArgs() == 3);
16769+
16770+
APValue Source, ShuffleMask;
16771+
APSInt ZeroMask;
16772+
if (!EvaluateVector(E->getArg(0), Source, Info) ||
16773+
!EvaluateVector(E->getArg(1), ShuffleMask, Info) ||
16774+
!EvaluateInteger(E->getArg(2), ZeroMask, Info))
16775+
return false;
16776+
16777+
assert(Source.getVectorLength() == ShuffleMask.getVectorLength());
16778+
assert(ZeroMask.getBitWidth() == Source.getVectorLength());
16779+
16780+
unsigned NumBytesInQWord = 8;
16781+
unsigned NumBitsInByte = 8;
16782+
unsigned NumBytes = Source.getVectorLength();
16783+
unsigned NumQWords = NumBytes / NumBytesInQWord;
16784+
unsigned RetWidth = ZeroMask.getBitWidth();
16785+
APSInt RetMask(llvm::APInt(RetWidth, 0), /*isUnsigned=*/true);
16786+
16787+
for (unsigned QWordId = 0; QWordId != NumQWords; ++QWordId) {
16788+
APInt SourceQWord(64, 0);
16789+
for (unsigned ByteIdx = 0; ByteIdx != NumBytesInQWord; ++ByteIdx) {
16790+
uint64_t Byte = Source.getVectorElt(QWordId * NumBytesInQWord + ByteIdx)
16791+
.getInt()
16792+
.getZExtValue();
16793+
SourceQWord.insertBits(APInt(8, Byte & 0xFF), ByteIdx * NumBitsInByte);
16794+
}
16795+
16796+
for (unsigned ByteIdx = 0; ByteIdx != NumBytesInQWord; ++ByteIdx) {
16797+
unsigned SelIdx = QWordId * NumBytesInQWord + ByteIdx;
16798+
unsigned M =
16799+
ShuffleMask.getVectorElt(SelIdx).getInt().getZExtValue() & 0x3F;
16800+
if (ZeroMask[SelIdx]) {
16801+
RetMask.setBitVal(SelIdx, SourceQWord[M]);
16802+
}
16803+
}
16804+
}
16805+
return Success(APValue(RetMask), E);
16806+
}
1676516807
}
1676616808
}
1676716809

‎clang/lib/Headers/avx512bitalgintrin.h‎

Lines changed: 11 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -15,44 +15,42 @@
1515
#define __AVX512BITALGINTRIN_H
1616

1717
/* Define the default attributes for the functions in this file. */
18+
#if defined(__cplusplus) && (__cplusplus >= 201103L)
1819
#define __DEFAULT_FN_ATTRS \
1920
__attribute__((__always_inline__, __nodebug__, __target__("avx512bitalg"), \
20-
__min_vector_width__(512)))
21-
22-
#if defined(__cplusplus) && (__cplusplus >= 201103L)
23-
#define __DEFAULT_FN_ATTRS_CONSTEXPR __DEFAULT_FN_ATTRS constexpr
21+
__min_vector_width__(512))) constexpr
2422
#else
25-
#define __DEFAULT_FN_ATTRS_CONSTEXPR __DEFAULT_FN_ATTRS
23+
#define __DEFAULT_FN_ATTRS \
24+
__attribute__((__always_inline__, __nodebug__, __target__("avx512bitalg"), \
25+
__min_vector_width__(512)))
2626
#endif
2727

28-
static __inline__ __m512i __DEFAULT_FN_ATTRS_CONSTEXPR
29-
_mm512_popcnt_epi16(__m512i __A) {
28+
static __inline__ __m512i __DEFAULT_FN_ATTRS _mm512_popcnt_epi16(__m512i __A) {
3029
return (__m512i)__builtin_elementwise_popcount((__v32hu)__A);
3130
}
3231

33-
static __inline__ __m512i __DEFAULT_FN_ATTRS_CONSTEXPR
32+
static __inline__ __m512i __DEFAULT_FN_ATTRS
3433
_mm512_mask_popcnt_epi16(__m512i __A, __mmask32 __U, __m512i __B) {
3534
return (__m512i)__builtin_ia32_selectw_512(
3635
(__mmask32)__U, (__v32hi)_mm512_popcnt_epi16(__B), (__v32hi)__A);
3736
}
3837

39-
static __inline__ __m512i __DEFAULT_FN_ATTRS_CONSTEXPR
38+
static __inline__ __m512i __DEFAULT_FN_ATTRS
4039
_mm512_maskz_popcnt_epi16(__mmask32 __U, __m512i __B) {
4140
return _mm512_mask_popcnt_epi16((__m512i)_mm512_setzero_si512(), __U, __B);
4241
}
4342

44-
static __inline__ __m512i __DEFAULT_FN_ATTRS_CONSTEXPR
45-
_mm512_popcnt_epi8(__m512i __A) {
43+
static __inline__ __m512i __DEFAULT_FN_ATTRS _mm512_popcnt_epi8(__m512i __A) {
4644
return (__m512i)__builtin_elementwise_popcount((__v64qu)__A);
4745
}
4846

49-
static __inline__ __m512i __DEFAULT_FN_ATTRS_CONSTEXPR
47+
static __inline__ __m512i __DEFAULT_FN_ATTRS
5048
_mm512_mask_popcnt_epi8(__m512i __A, __mmask64 __U, __m512i __B) {
5149
return (__m512i)__builtin_ia32_selectb_512(
5250
(__mmask64)__U, (__v64qi)_mm512_popcnt_epi8(__B), (__v64qi)__A);
5351
}
5452

55-
static __inline__ __m512i __DEFAULT_FN_ATTRS_CONSTEXPR
53+
static __inline__ __m512i __DEFAULT_FN_ATTRS
5654
_mm512_maskz_popcnt_epi8(__mmask64 __U, __m512i __B) {
5755
return _mm512_mask_popcnt_epi8((__m512i)_mm512_setzero_si512(), __U, __B);
5856
}
@@ -74,6 +72,4 @@ _mm512_bitshuffle_epi64_mask(__m512i __A, __m512i __B)
7472
}
7573

7674
#undef __DEFAULT_FN_ATTRS
77-
#undef __DEFAULT_FN_ATTRS_CONSTEXPR
78-
7975
#endif

‎clang/lib/Headers/avx512vlbitalgintrin.h‎

Lines changed: 22 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -15,6 +15,16 @@
1515
#define __AVX512VLBITALGINTRIN_H
1616

1717
/* Define the default attributes for the functions in this file. */
18+
#if defined(__cplusplus) && (__cplusplus >= 201103L)
19+
#define __DEFAULT_FN_ATTRS128 \
20+
__attribute__((__always_inline__, __nodebug__, \
21+
__target__("avx512vl,avx512bitalg"), \
22+
__min_vector_width__(128))) constexpr
23+
#define __DEFAULT_FN_ATTRS256 \
24+
__attribute__((__always_inline__, __nodebug__, \
25+
__target__("avx512vl,avx512bitalg"), \
26+
__min_vector_width__(256))) constexpr
27+
#else
1828
#define __DEFAULT_FN_ATTRS128 \
1929
__attribute__((__always_inline__, __nodebug__, \
2030
__target__("avx512vl,avx512bitalg"), \
@@ -23,75 +33,66 @@
2333
__attribute__((__always_inline__, __nodebug__, \
2434
__target__("avx512vl,avx512bitalg"), \
2535
__min_vector_width__(256)))
26-
27-
#if defined(__cplusplus) && (__cplusplus >= 201103L)
28-
#define __DEFAULT_FN_ATTRS128_CONSTEXPR __DEFAULT_FN_ATTRS128 constexpr
29-
#define __DEFAULT_FN_ATTRS256_CONSTEXPR __DEFAULT_FN_ATTRS256 constexpr
30-
#else
31-
#define __DEFAULT_FN_ATTRS128_CONSTEXPR __DEFAULT_FN_ATTRS128
32-
#define __DEFAULT_FN_ATTRS256_CONSTEXPR __DEFAULT_FN_ATTRS256
3336
#endif
3437

35-
static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR
38+
static __inline__ __m256i __DEFAULT_FN_ATTRS256
3639
_mm256_popcnt_epi16(__m256i __A) {
3740
return (__m256i)__builtin_elementwise_popcount((__v16hu)__A);
3841
}
3942

40-
static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR
43+
static __inline__ __m256i __DEFAULT_FN_ATTRS256
4144
_mm256_mask_popcnt_epi16(__m256i __A, __mmask16 __U, __m256i __B) {
4245
return (__m256i)__builtin_ia32_selectw_256(
4346
(__mmask16)__U, (__v16hi)_mm256_popcnt_epi16(__B), (__v16hi)__A);
4447
}
4548

46-
static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR
49+
static __inline__ __m256i __DEFAULT_FN_ATTRS256
4750
_mm256_maskz_popcnt_epi16(__mmask16 __U, __m256i __B) {
4851
return _mm256_mask_popcnt_epi16((__m256i)_mm256_setzero_si256(), __U, __B);
4952
}
5053

51-
static __inline__ __m128i __DEFAULT_FN_ATTRS128_CONSTEXPR
52-
_mm_popcnt_epi16(__m128i __A) {
54+
static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_popcnt_epi16(__m128i __A) {
5355
return (__m128i)__builtin_elementwise_popcount((__v8hu)__A);
5456
}
5557

56-
static __inline__ __m128i __DEFAULT_FN_ATTRS128_CONSTEXPR
58+
static __inline__ __m128i __DEFAULT_FN_ATTRS128
5759
_mm_mask_popcnt_epi16(__m128i __A, __mmask8 __U, __m128i __B) {
5860
return (__m128i)__builtin_ia32_selectw_128(
5961
(__mmask8)__U, (__v8hi)_mm_popcnt_epi16(__B), (__v8hi)__A);
6062
}
6163

62-
static __inline__ __m128i __DEFAULT_FN_ATTRS128_CONSTEXPR
64+
static __inline__ __m128i __DEFAULT_FN_ATTRS128
6365
_mm_maskz_popcnt_epi16(__mmask8 __U, __m128i __B) {
6466
return _mm_mask_popcnt_epi16((__m128i)_mm_setzero_si128(), __U, __B);
6567
}
6668

67-
static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR
69+
static __inline__ __m256i __DEFAULT_FN_ATTRS256
6870
_mm256_popcnt_epi8(__m256i __A) {
6971
return (__m256i)__builtin_elementwise_popcount((__v32qu)__A);
7072
}
7173

72-
static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR
74+
static __inline__ __m256i __DEFAULT_FN_ATTRS256
7375
_mm256_mask_popcnt_epi8(__m256i __A, __mmask32 __U, __m256i __B) {
7476
return (__m256i)__builtin_ia32_selectb_256(
7577
(__mmask32)__U, (__v32qi)_mm256_popcnt_epi8(__B), (__v32qi)__A);
7678
}
7779

78-
static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR
80+
static __inline__ __m256i __DEFAULT_FN_ATTRS256
7981
_mm256_maskz_popcnt_epi8(__mmask32 __U, __m256i __B) {
8082
return _mm256_mask_popcnt_epi8((__m256i)_mm256_setzero_si256(), __U, __B);
8183
}
8284

83-
static __inline__ __m128i __DEFAULT_FN_ATTRS128_CONSTEXPR
84-
_mm_popcnt_epi8(__m128i __A) {
85+
static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_popcnt_epi8(__m128i __A) {
8586
return (__m128i)__builtin_elementwise_popcount((__v16qu)__A);
8687
}
8788

88-
static __inline__ __m128i __DEFAULT_FN_ATTRS128_CONSTEXPR
89+
static __inline__ __m128i __DEFAULT_FN_ATTRS128
8990
_mm_mask_popcnt_epi8(__m128i __A, __mmask16 __U, __m128i __B) {
9091
return (__m128i)__builtin_ia32_selectb_128(
9192
(__mmask16)__U, (__v16qi)_mm_popcnt_epi8(__B), (__v16qi)__A);
9293
}
9394

94-
static __inline__ __m128i __DEFAULT_FN_ATTRS128_CONSTEXPR
95+
static __inline__ __m128i __DEFAULT_FN_ATTRS128
9596
_mm_maskz_popcnt_epi8(__mmask16 __U, __m128i __B) {
9697
return _mm_mask_popcnt_epi8((__m128i)_mm_setzero_si128(), __U, __B);
9798
}
@@ -131,7 +132,4 @@ _mm_bitshuffle_epi64_mask(__m128i __A, __m128i __B)
131132

132133
#undef __DEFAULT_FN_ATTRS128
133134
#undef __DEFAULT_FN_ATTRS256
134-
#undef __DEFAULT_FN_ATTRS128_CONSTEXPR
135-
#undef __DEFAULT_FN_ATTRS256_CONSTEXPR
136-
137135
#endif

‎clang/test/CodeGen/X86/avx512bitalg-builtins.c‎

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -70,4 +70,14 @@ __mmask64 test_mm512_bitshuffle_epi64_mask(__m512i __A, __m512i __B) {
7070
// CHECK: @llvm.x86.avx512.vpshufbitqmb.512
7171
return _mm512_bitshuffle_epi64_mask(__A, __B);
7272
}
73+
TEST_CONSTEXPR(_mm512_bitshuffle_epi64_mask(
74+
(__m512i)(__v64qi){1,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,-128, -1,0,0,0,0,0,0,0, 85,85,85,85,85,85,85,85,
75+
1,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,-128, -1,0,0,0,0,0,0,0, 85,85,85,85,85,85,85,85},
76+
(__m512i)(__v64qi){0,1,2,3,4,5,6,7, 63,62,61,60,59,58,57,56, 0,1,2,3,4,5,6,7, 0,1,2,3,4,5,6,7,
77+
0,1,2,3,4,5,6,7, 63,62,61,60,59,58,57,56, 0,1,2,3,4,5,6,7, 0,1,2,3,4,5,6,7}) == 0x55ff010155ff0101ULL);
7378

79+
TEST_CONSTEXPR(_mm512_mask_bitshuffle_epi64_mask(0xFFFFFFFF00000000ULL,
80+
(__m512i)(__v64qi){1,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,-128, -1,0,0,0,0,0,0,0, 85,85,85,85,85,85,85,85,
81+
1,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,-128, -1,0,0,0,0,0,0,0, 85,85,85,85,85,85,85,85},
82+
(__m512i)(__v64qi){0,1,2,3,4,5,6,7, 63,62,61,60,59,58,57,56, 0,1,2,3,4,5,6,7, 0,1,2,3,4,5,6,7,
83+
0,1,2,3,4,5,6,7, 63,62,61,60,59,58,57,56, 0,1,2,3,4,5,6,7, 0,1,2,3,4,5,6,7}) == 0x55ff010100000000ULL);

‎clang/test/CodeGen/X86/avx512vlbitalg-builtins.c‎

Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -116,6 +116,13 @@ __mmask32 test_mm256_bitshuffle_epi64_mask(__m256i __A, __m256i __B) {
116116
// CHECK: @llvm.x86.avx512.vpshufbitqmb.256
117117
return _mm256_bitshuffle_epi64_mask(__A, __B);
118118
}
119+
TEST_CONSTEXPR(_mm256_bitshuffle_epi64_mask(
120+
(__m256i)(__v32qi){1,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,-128, -1,0,0,0,0,0,0,0, 85,85,85,85,85,85,85,85},
121+
(__m256i)(__v32qi){0,1,2,3,4,5,6,7, 63,62,61,60,59,58,57,56, 0,1,2,3,4,5,6,7, 0,1,2,3,4,5,6,7}) == 0x55ff0101);
122+
123+
TEST_CONSTEXPR(_mm256_mask_bitshuffle_epi64_mask(0xFFFF0000,
124+
(__m256i)(__v32qi){1,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,-128, -1,0,0,0,0,0,0,0, 85,85,85,85,85,85,85,85},
125+
(__m256i)(__v32qi){0,1,2,3,4,5,6,7, 63,62,61,60,59,58,57,56, 0,1,2,3,4,5,6,7, 0,1,2,3,4,5,6,7}) == 0x55ff0000);
119126

120127
__mmask16 test_mm_mask_bitshuffle_epi64_mask(__mmask16 __U, __m128i __A, __m128i __B) {
121128
// CHECK-LABEL: test_mm_mask_bitshuffle_epi64_mask
@@ -129,4 +136,11 @@ __mmask16 test_mm_bitshuffle_epi64_mask(__m128i __A, __m128i __B) {
129136
// CHECK: @llvm.x86.avx512.vpshufbitqmb.128
130137
return _mm_bitshuffle_epi64_mask(__A, __B);
131138
}
139+
TEST_CONSTEXPR(_mm_bitshuffle_epi64_mask(
140+
(__m128i)(__v16qi){1,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,-128},
141+
(__m128i)(__v16qi){0,1,2,3,4,5,6,7, 63,62,61,60,59,58,57,56}) == 0x0101);
142+
143+
TEST_CONSTEXPR(_mm_mask_bitshuffle_epi64_mask(0xFF00,
144+
(__m128i)(__v16qi){1,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,-128},
145+
(__m128i)(__v16qi){0,1,2,3,4,5,6,7, 63,62,61,60,59,58,57,56}) == 0x0100);
132146

0 commit comments

Comments
 (0)