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bzEqKai Luo
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Kai Luo
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[Thumb2][ARMAsmParser] Fix processing of t2{LDR,STR}{*}_{PRE,POST}_imm when changing to its concrete form (llvm#116757)
`t2{LDR,STR}{*}_{PRE,POST}_imm` is pseudo instruction and is expected to be `t2{LDR,STR}{*}_{PRE,POST}`. During building the new MCInst of `t2{LDR,STR}{*}_{PRE,POST}`, the order of operands looks incorrect. Fixes llvm#97020. --------- Co-authored-by: Kai Luo <[email protected]>
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‎llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp‎

Lines changed: 16 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -9053,10 +9053,11 @@ bool ARMAsmParser::processInstruction(MCInst &Inst,
90539053
TmpInst.setOpcode(Inst.getOpcode() == ARM::t2LDR_PRE_imm ? ARM::t2LDR_PRE
90549054
: ARM::t2LDR_POST);
90559055
TmpInst.addOperand(Inst.getOperand(0)); // Rt
9056-
TmpInst.addOperand(Inst.getOperand(4)); // Rt_wb
9056+
TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb
90579057
TmpInst.addOperand(Inst.getOperand(1)); // Rn
90589058
TmpInst.addOperand(Inst.getOperand(2)); // imm
90599059
TmpInst.addOperand(Inst.getOperand(3)); // CondCode
9060+
TmpInst.addOperand(Inst.getOperand(4));
90609061
Inst = TmpInst;
90619062
return true;
90629063
}
@@ -9066,11 +9067,12 @@ bool ARMAsmParser::processInstruction(MCInst &Inst,
90669067
MCInst TmpInst;
90679068
TmpInst.setOpcode(Inst.getOpcode() == ARM::t2STR_PRE_imm ? ARM::t2STR_PRE
90689069
: ARM::t2STR_POST);
9069-
TmpInst.addOperand(Inst.getOperand(4)); // Rt_wb
9070+
TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb
90709071
TmpInst.addOperand(Inst.getOperand(0)); // Rt
90719072
TmpInst.addOperand(Inst.getOperand(1)); // Rn
90729073
TmpInst.addOperand(Inst.getOperand(2)); // imm
90739074
TmpInst.addOperand(Inst.getOperand(3)); // CondCode
9075+
TmpInst.addOperand(Inst.getOperand(4));
90749076
Inst = TmpInst;
90759077
return true;
90769078
}
@@ -9092,10 +9094,11 @@ bool ARMAsmParser::processInstruction(MCInst &Inst,
90929094
? ARM::t2LDRB_PRE
90939095
: ARM::t2LDRB_POST);
90949096
TmpInst.addOperand(Inst.getOperand(0)); // Rt
9095-
TmpInst.addOperand(Inst.getOperand(4)); // Rt_wb
9097+
TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb
90969098
TmpInst.addOperand(Inst.getOperand(1)); // Rn
90979099
TmpInst.addOperand(Inst.getOperand(2)); // imm
90989100
TmpInst.addOperand(Inst.getOperand(3)); // CondCode
9101+
TmpInst.addOperand(Inst.getOperand(4));
90999102
Inst = TmpInst;
91009103
return true;
91019104
}
@@ -9116,11 +9119,12 @@ bool ARMAsmParser::processInstruction(MCInst &Inst,
91169119
TmpInst.setOpcode(Inst.getOpcode() == ARM::t2STRB_PRE_imm
91179120
? ARM::t2STRB_PRE
91189121
: ARM::t2STRB_POST);
9119-
TmpInst.addOperand(Inst.getOperand(4)); // Rt_wb
9122+
TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb
91209123
TmpInst.addOperand(Inst.getOperand(0)); // Rt
91219124
TmpInst.addOperand(Inst.getOperand(1)); // Rn
91229125
TmpInst.addOperand(Inst.getOperand(2)); // imm
91239126
TmpInst.addOperand(Inst.getOperand(3)); // CondCode
9127+
TmpInst.addOperand(Inst.getOperand(4));
91249128
Inst = TmpInst;
91259129
return true;
91269130
}
@@ -9142,10 +9146,11 @@ bool ARMAsmParser::processInstruction(MCInst &Inst,
91429146
? ARM::t2LDRH_PRE
91439147
: ARM::t2LDRH_POST);
91449148
TmpInst.addOperand(Inst.getOperand(0)); // Rt
9145-
TmpInst.addOperand(Inst.getOperand(4)); // Rt_wb
9149+
TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb
91469150
TmpInst.addOperand(Inst.getOperand(1)); // Rn
91479151
TmpInst.addOperand(Inst.getOperand(2)); // imm
91489152
TmpInst.addOperand(Inst.getOperand(3)); // CondCode
9153+
TmpInst.addOperand(Inst.getOperand(4));
91499154
Inst = TmpInst;
91509155
return true;
91519156
}
@@ -9166,11 +9171,12 @@ bool ARMAsmParser::processInstruction(MCInst &Inst,
91669171
TmpInst.setOpcode(Inst.getOpcode() == ARM::t2STRH_PRE_imm
91679172
? ARM::t2STRH_PRE
91689173
: ARM::t2STRH_POST);
9169-
TmpInst.addOperand(Inst.getOperand(4)); // Rt_wb
9174+
TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb
91709175
TmpInst.addOperand(Inst.getOperand(0)); // Rt
91719176
TmpInst.addOperand(Inst.getOperand(1)); // Rn
91729177
TmpInst.addOperand(Inst.getOperand(2)); // imm
91739178
TmpInst.addOperand(Inst.getOperand(3)); // CondCode
9179+
TmpInst.addOperand(Inst.getOperand(4));
91749180
Inst = TmpInst;
91759181
return true;
91769182
}
@@ -9192,10 +9198,11 @@ bool ARMAsmParser::processInstruction(MCInst &Inst,
91929198
? ARM::t2LDRSB_PRE
91939199
: ARM::t2LDRSB_POST);
91949200
TmpInst.addOperand(Inst.getOperand(0)); // Rt
9195-
TmpInst.addOperand(Inst.getOperand(4)); // Rt_wb
9201+
TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb
91969202
TmpInst.addOperand(Inst.getOperand(1)); // Rn
91979203
TmpInst.addOperand(Inst.getOperand(2)); // imm
91989204
TmpInst.addOperand(Inst.getOperand(3)); // CondCode
9205+
TmpInst.addOperand(Inst.getOperand(4));
91999206
Inst = TmpInst;
92009207
return true;
92019208
}
@@ -9217,10 +9224,11 @@ bool ARMAsmParser::processInstruction(MCInst &Inst,
92179224
? ARM::t2LDRSH_PRE
92189225
: ARM::t2LDRSH_POST);
92199226
TmpInst.addOperand(Inst.getOperand(0)); // Rt
9220-
TmpInst.addOperand(Inst.getOperand(4)); // Rt_wb
9227+
TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb
92219228
TmpInst.addOperand(Inst.getOperand(1)); // Rn
92229229
TmpInst.addOperand(Inst.getOperand(2)); // imm
92239230
TmpInst.addOperand(Inst.getOperand(3)); // CondCode
9231+
TmpInst.addOperand(Inst.getOperand(4));
92249232
Inst = TmpInst;
92259233
return true;
92269234
}

‎llvm/test/tools/llvm-mca/ARM/m4-ldr-str-w.s‎

Lines changed: 80 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,80 @@
1+
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
2+
# RUN: llvm-mca -mtriple thumbv7m-none-eabi -mcpu=cortex-m4 < %s | FileCheck %s
3+
str.w r1, [r0], #16
4+
str.w r1, [r0, 16]!
5+
strb.w r1, [r0], #16
6+
strb.w r1, [r0, 16]!
7+
strh.w r1, [r0], #16
8+
strh.w r1, [r0, 16]!
9+
ldr.w r1, [r0], #16
10+
ldr.w r1, [r0, 16]!
11+
ldrb.w r1, [r0], #16
12+
ldrb.w r1, [r0, 16]!
13+
ldrh.w r1, [r0], #16
14+
ldrh.w r1, [r0, 16]!
15+
ldrsb.w r1, [r0], #16
16+
ldrsb.w r1, [r0, 16]!
17+
ldrsh.w r1, [r0], #16
18+
ldrsh.w r1, [r0, 16]!
19+
20+
# CHECK: Iterations: 100
21+
# CHECK-NEXT: Instructions: 1600
22+
# CHECK-NEXT: Total Cycles: 2601
23+
# CHECK-NEXT: Total uOps: 1600
24+
25+
# CHECK: Dispatch Width: 1
26+
# CHECK-NEXT: uOps Per Cycle: 0.62
27+
# CHECK-NEXT: IPC: 0.62
28+
# CHECK-NEXT: Block RThroughput: 16.0
29+
30+
# CHECK: Instruction Info:
31+
# CHECK-NEXT: [1]: #uOps
32+
# CHECK-NEXT: [2]: Latency
33+
# CHECK-NEXT: [3]: RThroughput
34+
# CHECK-NEXT: [4]: MayLoad
35+
# CHECK-NEXT: [5]: MayStore
36+
# CHECK-NEXT: [6]: HasSideEffects (U)
37+
38+
# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
39+
# CHECK-NEXT: 1 1 1.00 * str r1, [r0], #16
40+
# CHECK-NEXT: 1 1 1.00 * str r1, [r0, #16]!
41+
# CHECK-NEXT: 1 1 1.00 * strb r1, [r0], #16
42+
# CHECK-NEXT: 1 1 1.00 * strb r1, [r0, #16]!
43+
# CHECK-NEXT: 1 1 1.00 * strh r1, [r0], #16
44+
# CHECK-NEXT: 1 1 1.00 * strh r1, [r0, #16]!
45+
# CHECK-NEXT: 1 2 1.00 * ldr r1, [r0], #16
46+
# CHECK-NEXT: 1 2 1.00 * ldr r1, [r0, #16]!
47+
# CHECK-NEXT: 1 2 1.00 * ldrb r1, [r0], #16
48+
# CHECK-NEXT: 1 2 1.00 * ldrb r1, [r0, #16]!
49+
# CHECK-NEXT: 1 2 1.00 * ldrh r1, [r0], #16
50+
# CHECK-NEXT: 1 2 1.00 * ldrh r1, [r0, #16]!
51+
# CHECK-NEXT: 1 2 1.00 * ldrsb r1, [r0], #16
52+
# CHECK-NEXT: 1 2 1.00 * ldrsb r1, [r0, #16]!
53+
# CHECK-NEXT: 1 2 1.00 * ldrsh r1, [r0], #16
54+
# CHECK-NEXT: 1 2 1.00 * ldrsh r1, [r0, #16]!
55+
56+
# CHECK: Resources:
57+
# CHECK-NEXT: [0] - M4Unit
58+
59+
# CHECK: Resource pressure per iteration:
60+
# CHECK-NEXT: [0]
61+
# CHECK-NEXT: 16.00
62+
63+
# CHECK: Resource pressure by instruction:
64+
# CHECK-NEXT: [0] Instructions:
65+
# CHECK-NEXT: 1.00 str r1, [r0], #16
66+
# CHECK-NEXT: 1.00 str r1, [r0, #16]!
67+
# CHECK-NEXT: 1.00 strb r1, [r0], #16
68+
# CHECK-NEXT: 1.00 strb r1, [r0, #16]!
69+
# CHECK-NEXT: 1.00 strh r1, [r0], #16
70+
# CHECK-NEXT: 1.00 strh r1, [r0, #16]!
71+
# CHECK-NEXT: 1.00 ldr r1, [r0], #16
72+
# CHECK-NEXT: 1.00 ldr r1, [r0, #16]!
73+
# CHECK-NEXT: 1.00 ldrb r1, [r0], #16
74+
# CHECK-NEXT: 1.00 ldrb r1, [r0, #16]!
75+
# CHECK-NEXT: 1.00 ldrh r1, [r0], #16
76+
# CHECK-NEXT: 1.00 ldrh r1, [r0, #16]!
77+
# CHECK-NEXT: 1.00 ldrsb r1, [r0], #16
78+
# CHECK-NEXT: 1.00 ldrsb r1, [r0, #16]!
79+
# CHECK-NEXT: 1.00 ldrsh r1, [r0], #16
80+
# CHECK-NEXT: 1.00 ldrsh r1, [r0, #16]!

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