[FastISel] Use Register. NFC

This focuses on the common interfaces and tablegen. More changes
are needed to individual targets.

Author: topperc

llvm/include/llvm/CodeGen/FastISel.h

@@ -348,21 +348,21 @@ class FastISel {
 
   /// This method is called by target-independent code to request that an
   /// instruction with the given type and opcode be emitted.
-  virtual unsigned fastEmit_(MVT VT, MVT RetVT, unsigned Opcode);
+  virtual Register fastEmit_(MVT VT, MVT RetVT, unsigned Opcode);
 
   /// This method is called by target-independent code to request that an
   /// instruction with the given type, opcode, and register operand be emitted.
-  virtual unsigned fastEmit_r(MVT VT, MVT RetVT, unsigned Opcode, Register Op0);
+  virtual Register fastEmit_r(MVT VT, MVT RetVT, unsigned Opcode, Register Op0);
 
   /// This method is called by target-independent code to request that an
   /// instruction with the given type, opcode, and register operands be emitted.
-  virtual unsigned fastEmit_rr(MVT VT, MVT RetVT, unsigned Opcode, Register Op0,
+  virtual Register fastEmit_rr(MVT VT, MVT RetVT, unsigned Opcode, Register Op0,
                                Register Op1);
 
   /// This method is called by target-independent code to request that an
   /// instruction with the given type, opcode, and register and immediate
   /// operands be emitted.
-  virtual unsigned fastEmit_ri(MVT VT, MVT RetVT, unsigned Opcode, Register Op0,
+  virtual Register fastEmit_ri(MVT VT, MVT RetVT, unsigned Opcode, Register Op0,
                                uint64_t Imm);
 
   /// This method is a wrapper of fastEmit_ri.
@@ -375,12 +375,12 @@ class FastISel {
 
   /// This method is called by target-independent code to request that an
   /// instruction with the given type, opcode, and immediate operand be emitted.
-  virtual unsigned fastEmit_i(MVT VT, MVT RetVT, unsigned Opcode, uint64_t Imm);
+  virtual Register fastEmit_i(MVT VT, MVT RetVT, unsigned Opcode, uint64_t Imm);
 
   /// This method is called by target-independent code to request that an
   /// instruction with the given type, opcode, and floating-point immediate
   /// operand be emitted.
-  virtual unsigned fastEmit_f(MVT VT, MVT RetVT, unsigned Opcode,
+  virtual Register fastEmit_f(MVT VT, MVT RetVT, unsigned Opcode,
                               const ConstantFP *FPImm);
 
   /// Emit a MachineInstr with no operands and a result register in the
@@ -470,15 +470,19 @@ class FastISel {
 
   /// Emit a constant in a register using target-specific logic, such as
   /// constant pool loads.
-  virtual unsigned fastMaterializeConstant(const Constant *C) { return 0; }
+  virtual Register fastMaterializeConstant(const Constant *C) {
+    return Register();
+  }
 
   /// Emit an alloca address in a register using target-specific logic.
-  virtual unsigned fastMaterializeAlloca(const AllocaInst *C) { return 0; }
+  virtual Register fastMaterializeAlloca(const AllocaInst *C) {
+    return Register();
+  }
 
   /// Emit the floating-point constant +0.0 in a register using target-
   /// specific logic.
-  virtual unsigned fastMaterializeFloatZero(const ConstantFP *CF) {
-    return 0;
+  virtual Register fastMaterializeFloatZero(const ConstantFP *CF) {
+    return Register();
   }
 
   /// Check if \c Add is an add that can be safely folded into \c GEP.

llvm/lib/CodeGen/SelectionDAG/FastISel.cpp

@@ -156,7 +156,8 @@ bool FastISel::lowerArguments() {
 }
 
 /// Return the defined register if this instruction defines exactly one
-/// virtual register and uses no other virtual registers. Otherwise return 0.
+/// virtual register and uses no other virtual registers. Otherwise return
+/// Register();
 static Register findLocalRegDef(MachineInstr &MI) {
   Register RegDef;
   for (const MachineOperand &MO : MI.operands()) {
@@ -315,7 +316,7 @@ Register FastISel::materializeConstant(const Value *V, MVT VT) {
     if (!selectOperator(Op, Op->getOpcode()))
       if (!isa<Instruction>(Op) ||
           !fastSelectInstruction(cast<Instruction>(Op)))
-        return 0;
+        return Register();
     Reg = lookUpRegForValue(Op);
   } else if (isa<UndefValue>(V)) {
     Reg = createResultReg(TLI.getRegClassFor(VT));
@@ -1950,29 +1951,29 @@ bool FastISel::fastLowerIntrinsicCall(const IntrinsicInst * /*II*/) {
   return false;
 }
 
-unsigned FastISel::fastEmit_(MVT, MVT, unsigned) { return 0; }
+Register FastISel::fastEmit_(MVT, MVT, unsigned) { return Register(); }
 
-unsigned FastISel::fastEmit_r(MVT, MVT, unsigned, Register /*Op0*/) {
-  return 0;
+Register FastISel::fastEmit_r(MVT, MVT, unsigned, Register /*Op0*/) {
+  return Register();
 }
 
-unsigned FastISel::fastEmit_rr(MVT, MVT, unsigned, Register /*Op0*/,
+Register FastISel::fastEmit_rr(MVT, MVT, unsigned, Register /*Op0*/,
                                Register /*Op1*/) {
-  return 0;
+  return Register();
 }
 
-unsigned FastISel::fastEmit_i(MVT, MVT, unsigned, uint64_t /*Imm*/) {
-  return 0;
+Register FastISel::fastEmit_i(MVT, MVT, unsigned, uint64_t /*Imm*/) {
+  return Register();
 }
 
-unsigned FastISel::fastEmit_f(MVT, MVT, unsigned,
+Register FastISel::fastEmit_f(MVT, MVT, unsigned,
                               const ConstantFP * /*FPImm*/) {
-  return 0;
+  return Register();
 }
 
-unsigned FastISel::fastEmit_ri(MVT, MVT, unsigned, Register /*Op0*/,
+Register FastISel::fastEmit_ri(MVT, MVT, unsigned, Register /*Op0*/,
                                uint64_t /*Imm*/) {
-  return 0;
+  return Register();
 }
 
 /// This method is a wrapper of fastEmit_ri. It first tries to emit an
@@ -1995,7 +1996,7 @@ Register FastISel::fastEmit_ri_(MVT VT, unsigned Opcode, Register Op0,
   // in-range.
   if ((Opcode == ISD::SHL || Opcode == ISD::SRA || Opcode == ISD::SRL) &&
       Imm >= VT.getSizeInBits())
-    return 0;
+    return Register();
 
   // First check if immediate type is legal. If not, we can't use the ri form.
   Register ResultReg = fastEmit_ri(VT, VT, Opcode, Op0, Imm);
@@ -2009,7 +2010,7 @@ Register FastISel::fastEmit_ri_(MVT VT, unsigned Opcode, Register Op0,
         IntegerType::get(FuncInfo.Fn->getContext(), VT.getSizeInBits());
     MaterialReg = getRegForValue(ConstantInt::get(ITy, Imm));
     if (!MaterialReg)
-      return 0;
+      return Register();
   }
   return fastEmit_rr(VT, VT, Opcode, Op0, MaterialReg);
 }

llvm/lib/Target/AArch64/AArch64FastISel.cpp

@@ -277,9 +277,9 @@ class AArch64FastISel final : public FastISel {
 
 public:
   // Backend specific FastISel code.
-  unsigned fastMaterializeAlloca(const AllocaInst *AI) override;
-  unsigned fastMaterializeConstant(const Constant *C) override;
-  unsigned fastMaterializeFloatZero(const ConstantFP* CF) override;
+  Register fastMaterializeAlloca(const AllocaInst *AI) override;
+  Register fastMaterializeConstant(const Constant *C) override;
+  Register fastMaterializeFloatZero(const ConstantFP *CF) override;
 
   explicit AArch64FastISel(FunctionLoweringInfo &FuncInfo,
                            const TargetLibraryInfo *LibInfo)
@@ -346,13 +346,13 @@ CCAssignFn *AArch64FastISel::CCAssignFnForCall(CallingConv::ID CC) const {
   return CC_AArch64_AAPCS;
 }
 
-unsigned AArch64FastISel::fastMaterializeAlloca(const AllocaInst *AI) {
+Register AArch64FastISel::fastMaterializeAlloca(const AllocaInst *AI) {
   assert(TLI.getValueType(DL, AI->getType(), true) == MVT::i64 &&
          "Alloca should always return a pointer.");
 
   // Don't handle dynamic allocas.
   if (!FuncInfo.StaticAllocaMap.count(AI))
-    return 0;
+    return Register();
 
   DenseMap<const AllocaInst *, int>::iterator SI =
       FuncInfo.StaticAllocaMap.find(AI);
@@ -367,7 +367,7 @@ unsigned AArch64FastISel::fastMaterializeAlloca(const AllocaInst *AI) {
     return ResultReg;
   }
 
-  return 0;
+  return Register();
 }
 
 unsigned AArch64FastISel::materializeInt(const ConstantInt *CI, MVT VT) {
@@ -537,12 +537,12 @@ unsigned AArch64FastISel::materializeGV(const GlobalValue *GV) {
   return ResultReg;
 }
 
-unsigned AArch64FastISel::fastMaterializeConstant(const Constant *C) {
+Register AArch64FastISel::fastMaterializeConstant(const Constant *C) {
   EVT CEVT = TLI.getValueType(DL, C->getType(), true);
 
   // Only handle simple types.
   if (!CEVT.isSimple())
-    return 0;
+    return Register();
   MVT VT = CEVT.getSimpleVT();
   // arm64_32 has 32-bit pointers held in 64-bit registers. Because of that,
   // 'null' pointers need to have a somewhat special treatment.
@@ -558,18 +558,18 @@ unsigned AArch64FastISel::fastMaterializeConstant(const Constant *C) {
   else if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
     return materializeGV(GV);
 
-  return 0;
+  return Register();
 }
 
-unsigned AArch64FastISel::fastMaterializeFloatZero(const ConstantFP* CFP) {
+Register AArch64FastISel::fastMaterializeFloatZero(const ConstantFP *CFP) {
   assert(CFP->isNullValue() &&
          "Floating-point constant is not a positive zero.");
   MVT VT;
   if (!isTypeLegal(CFP->getType(), VT))
-    return 0;
+    return Register();
 
   if (VT != MVT::f32 && VT != MVT::f64)
-    return 0;
+    return Register();
 
   bool Is64Bit = (VT == MVT::f64);
   unsigned ZReg = Is64Bit ? AArch64::XZR : AArch64::WZR;

llvm/lib/Target/ARM/ARMFastISel.cpp

@@ -147,8 +147,8 @@ class ARMFastISel final : public FastISel {
     // Backend specific FastISel code.
 
     bool fastSelectInstruction(const Instruction *I) override;
-    unsigned fastMaterializeConstant(const Constant *C) override;
-    unsigned fastMaterializeAlloca(const AllocaInst *AI) override;
+    Register fastMaterializeConstant(const Constant *C) override;
+    Register fastMaterializeAlloca(const AllocaInst *AI) override;
     bool tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo,
                              const LoadInst *LI) override;
     bool fastLowerArguments() override;
@@ -619,11 +619,12 @@ unsigned ARMFastISel::ARMMaterializeGV(const GlobalValue *GV, MVT VT) {
   return DestReg;
 }
 
-unsigned ARMFastISel::fastMaterializeConstant(const Constant *C) {
+Register ARMFastISel::fastMaterializeConstant(const Constant *C) {
   EVT CEVT = TLI.getValueType(DL, C->getType(), true);
 
   // Only handle simple types.
-  if (!CEVT.isSimple()) return 0;
+  if (!CEVT.isSimple())
+    return Register();
   MVT VT = CEVT.getSimpleVT();
 
   if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
@@ -633,17 +634,19 @@ unsigned ARMFastISel::fastMaterializeConstant(const Constant *C) {
   else if (isa<ConstantInt>(C))
     return ARMMaterializeInt(C, VT);
 
-  return 0;
+  return Register();
 }
 
 // TODO: unsigned ARMFastISel::TargetMaterializeFloatZero(const ConstantFP *CF);
 
-unsigned ARMFastISel::fastMaterializeAlloca(const AllocaInst *AI) {
+Register ARMFastISel::fastMaterializeAlloca(const AllocaInst *AI) {
   // Don't handle dynamic allocas.
-  if (!FuncInfo.StaticAllocaMap.count(AI)) return 0;
+  if (!FuncInfo.StaticAllocaMap.count(AI))
+    return Register();
 
   MVT VT;
-  if (!isLoadTypeLegal(AI->getType(), VT)) return 0;
+  if (!isLoadTypeLegal(AI->getType(), VT))
+    return Register();
 
   DenseMap<const AllocaInst*, int>::iterator SI =
     FuncInfo.StaticAllocaMap.find(AI);
@@ -663,7 +666,7 @@ unsigned ARMFastISel::fastMaterializeAlloca(const AllocaInst *AI) {
     return ResultReg;
   }
 
-  return 0;
+  return Register();
 }
 
 bool ARMFastISel::isTypeLegal(Type *Ty, MVT &VT) {

llvm/lib/Target/Mips/MipsFastISel.cpp

@@ -255,8 +255,8 @@ class MipsFastISel final : public FastISel {
     UnsupportedFPMode = Subtarget->isFP64bit() || Subtarget->useSoftFloat();
   }
 
-  unsigned fastMaterializeAlloca(const AllocaInst *AI) override;
-  unsigned fastMaterializeConstant(const Constant *C) override;
+  Register fastMaterializeAlloca(const AllocaInst *AI) override;
+  Register fastMaterializeConstant(const Constant *C) override;
   bool fastSelectInstruction(const Instruction *I) override;
 
 #include "MipsGenFastISel.inc"
@@ -327,7 +327,7 @@ unsigned MipsFastISel::emitLogicalOp(unsigned ISDOpc, MVT RetVT,
   return ResultReg;
 }
 
-unsigned MipsFastISel::fastMaterializeAlloca(const AllocaInst *AI) {
+Register MipsFastISel::fastMaterializeAlloca(const AllocaInst *AI) {
   assert(TLI.getValueType(DL, AI->getType(), true) == MVT::i32 &&
          "Alloca should always return a pointer.");
 
@@ -343,7 +343,7 @@ unsigned MipsFastISel::fastMaterializeAlloca(const AllocaInst *AI) {
     return ResultReg;
   }
 
-  return 0;
+  return Register();
 }
 
 unsigned MipsFastISel::materializeInt(const Constant *C, MVT VT) {
@@ -437,12 +437,12 @@ unsigned MipsFastISel::materializeExternalCallSym(MCSymbol *Sym) {
 
 // Materialize a constant into a register, and return the register
 // number (or zero if we failed to handle it).
-unsigned MipsFastISel::fastMaterializeConstant(const Constant *C) {
+Register MipsFastISel::fastMaterializeConstant(const Constant *C) {
   EVT CEVT = TLI.getValueType(DL, C->getType(), true);
 
   // Only handle simple types.
   if (!CEVT.isSimple())
-    return 0;
+    return Register();
   MVT VT = CEVT.getSimpleVT();
 
   if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
@@ -452,7 +452,7 @@ unsigned MipsFastISel::fastMaterializeConstant(const Constant *C) {
   else if (isa<ConstantInt>(C))
     return materializeInt(C, VT);
 
-  return 0;
+  return Register();
 }
 
 bool MipsFastISel::computeAddress(const Value *Obj, Address &Addr) {