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RKSimonRKSimon
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[X86] Add missing immediate qualifier to the (V)INSERT/EXTRACT/PERM2 instruction names (llvm#108593)
Makes it easier to algorithmically recreate the instruction name in various analysis scripts I'm working on
1 parent 87663fd commit 614a064

33 files changed

+302
-301
lines changed

‎llvm/lib/Target/X86/GISel/X86InstructionSelector.cpp‎

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1255,16 +1255,16 @@ bool X86InstructionSelector::selectExtract(MachineInstr &I,
12551255

12561256
if (SrcTy.getSizeInBits() == 256 && DstTy.getSizeInBits() == 128) {
12571257
if (HasVLX)
1258-
I.setDesc(TII.get(X86::VEXTRACTF32x4Z256rr));
1258+
I.setDesc(TII.get(X86::VEXTRACTF32x4Z256rri));
12591259
else if (HasAVX)
1260-
I.setDesc(TII.get(X86::VEXTRACTF128rr));
1260+
I.setDesc(TII.get(X86::VEXTRACTF128rri));
12611261
else
12621262
return false;
12631263
} else if (SrcTy.getSizeInBits() == 512 && HasAVX512) {
12641264
if (DstTy.getSizeInBits() == 128)
1265-
I.setDesc(TII.get(X86::VEXTRACTF32x4Zrr));
1265+
I.setDesc(TII.get(X86::VEXTRACTF32x4Zrri));
12661266
else if (DstTy.getSizeInBits() == 256)
1267-
I.setDesc(TII.get(X86::VEXTRACTF64x4Zrr));
1267+
I.setDesc(TII.get(X86::VEXTRACTF64x4Zrri));
12681268
else
12691269
return false;
12701270
} else
@@ -1388,16 +1388,16 @@ bool X86InstructionSelector::selectInsert(MachineInstr &I,
13881388

13891389
if (DstTy.getSizeInBits() == 256 && InsertRegTy.getSizeInBits() == 128) {
13901390
if (HasVLX)
1391-
I.setDesc(TII.get(X86::VINSERTF32x4Z256rr));
1391+
I.setDesc(TII.get(X86::VINSERTF32x4Z256rri));
13921392
else if (HasAVX)
1393-
I.setDesc(TII.get(X86::VINSERTF128rr));
1393+
I.setDesc(TII.get(X86::VINSERTF128rri));
13941394
else
13951395
return false;
13961396
} else if (DstTy.getSizeInBits() == 512 && HasAVX512) {
13971397
if (InsertRegTy.getSizeInBits() == 128)
1398-
I.setDesc(TII.get(X86::VINSERTF32x4Zrr));
1398+
I.setDesc(TII.get(X86::VINSERTF32x4Zrri));
13991399
else if (InsertRegTy.getSizeInBits() == 256)
1400-
I.setDesc(TII.get(X86::VINSERTF64x4Zrr));
1400+
I.setDesc(TII.get(X86::VINSERTF64x4Zrri));
14011401
else
14021402
return false;
14031403
} else

‎llvm/lib/Target/X86/MCTargetDesc/X86InstComments.cpp‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1158,13 +1158,13 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
11581158
DestName = getRegName(MI->getOperand(0).getReg());
11591159
break;
11601160

1161-
case X86::VPERM2F128rr:
1162-
case X86::VPERM2I128rr:
1161+
case X86::VPERM2F128rri:
1162+
case X86::VPERM2I128rri:
11631163
Src2Name = getRegName(MI->getOperand(2).getReg());
11641164
[[fallthrough]];
11651165

1166-
case X86::VPERM2F128rm:
1167-
case X86::VPERM2I128rm:
1166+
case X86::VPERM2F128rmi:
1167+
case X86::VPERM2I128rmi:
11681168
// For instruction comments purpose, assume the 256-bit vector is v4i64.
11691169
if (MI->getOperand(NumOperands - 1).isImm())
11701170
DecodeVPERM2X128Mask(4, MI->getOperand(NumOperands - 1).getImm(),

‎llvm/lib/Target/X86/X86CompressEVEX.cpp‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -138,8 +138,8 @@ static bool performCustomAdjustments(MachineInstr &MI, unsigned NewOpc) {
138138
case X86::VSHUFI32X4Z256rri:
139139
case X86::VSHUFI64X2Z256rmi:
140140
case X86::VSHUFI64X2Z256rri: {
141-
assert((NewOpc == X86::VPERM2F128rr || NewOpc == X86::VPERM2I128rr ||
142-
NewOpc == X86::VPERM2F128rm || NewOpc == X86::VPERM2I128rm) &&
141+
assert((NewOpc == X86::VPERM2F128rri || NewOpc == X86::VPERM2I128rri ||
142+
NewOpc == X86::VPERM2F128rmi || NewOpc == X86::VPERM2I128rmi) &&
143143
"Unexpected new opcode!");
144144
MachineOperand &Imm = MI.getOperand(MI.getNumExplicitOperands() - 1);
145145
int64_t ImmVal = Imm.getImm();

‎llvm/lib/Target/X86/X86InstrAVX512.td‎

Lines changed: 29 additions & 29 deletions
Original file line numberDiff line numberDiff line change
@@ -368,7 +368,7 @@ multiclass vinsert_for_size_split<int Opcode, X86VectorVTInfo From,
368368
SDPatternOperator vinsert_for_mask,
369369
X86FoldableSchedWrite sched> {
370370
let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
371-
defm rr : AVX512_maskable_split<Opcode, MRMSrcReg, To, (outs To.RC:$dst),
371+
defm rri : AVX512_maskable_split<Opcode, MRMSrcReg, To, (outs To.RC:$dst),
372372
(ins To.RC:$src1, From.RC:$src2, u8imm:$src3),
373373
"vinsert" # From.EltTypeName # "x" # From.NumElts,
374374
"$src3, $src2, $src1", "$src1, $src2, $src3",
@@ -380,7 +380,7 @@ multiclass vinsert_for_size_split<int Opcode, X86VectorVTInfo From,
380380
(iPTR imm))>,
381381
AVX512AIi8Base, EVEX, VVVV, Sched<[sched]>;
382382
let mayLoad = 1 in
383-
defm rm : AVX512_maskable_split<Opcode, MRMSrcMem, To, (outs To.RC:$dst),
383+
defm rmi : AVX512_maskable_split<Opcode, MRMSrcMem, To, (outs To.RC:$dst),
384384
(ins To.RC:$src1, From.MemOp:$src2, u8imm:$src3),
385385
"vinsert" # From.EltTypeName # "x" # From.NumElts,
386386
"$src3, $src2, $src1", "$src1, $src2, $src3",
@@ -408,15 +408,15 @@ multiclass vinsert_for_size_lowering<string InstrStr, X86VectorVTInfo From,
408408
let Predicates = p in {
409409
def : Pat<(vinsert_insert:$ins
410410
(To.VT To.RC:$src1), (From.VT From.RC:$src2), (iPTR imm)),
411-
(To.VT (!cast<Instruction>(InstrStr#"rr")
411+
(To.VT (!cast<Instruction>(InstrStr#"rri")
412412
To.RC:$src1, From.RC:$src2,
413413
(INSERT_get_vinsert_imm To.RC:$ins)))>;
414414

415415
def : Pat<(vinsert_insert:$ins
416416
(To.VT To.RC:$src1),
417417
(From.VT (From.LdFrag addr:$src2)),
418418
(iPTR imm)),
419-
(To.VT (!cast<Instruction>(InstrStr#"rm")
419+
(To.VT (!cast<Instruction>(InstrStr#"rmi")
420420
To.RC:$src1, addr:$src2,
421421
(INSERT_get_vinsert_imm To.RC:$ins)))>;
422422
}
@@ -529,7 +529,7 @@ let Predicates = p in {
529529
(From.VT From.RC:$src2),
530530
(iPTR imm))),
531531
Cast.RC:$src0)),
532-
(!cast<Instruction>(InstrStr#"rrk")
532+
(!cast<Instruction>(InstrStr#"rrik")
533533
Cast.RC:$src0, Cast.KRCWM:$mask, To.RC:$src1, From.RC:$src2,
534534
(INSERT_get_vinsert_imm To.RC:$ins))>;
535535
def : Pat<(Cast.VT
@@ -541,7 +541,7 @@ let Predicates = p in {
541541
(From.LdFrag addr:$src2))),
542542
(iPTR imm))),
543543
Cast.RC:$src0)),
544-
(!cast<Instruction>(InstrStr#"rmk")
544+
(!cast<Instruction>(InstrStr#"rmik")
545545
Cast.RC:$src0, Cast.KRCWM:$mask, To.RC:$src1, addr:$src2,
546546
(INSERT_get_vinsert_imm To.RC:$ins))>;
547547

@@ -552,7 +552,7 @@ let Predicates = p in {
552552
(From.VT From.RC:$src2),
553553
(iPTR imm))),
554554
Cast.ImmAllZerosV)),
555-
(!cast<Instruction>(InstrStr#"rrkz")
555+
(!cast<Instruction>(InstrStr#"rrikz")
556556
Cast.KRCWM:$mask, To.RC:$src1, From.RC:$src2,
557557
(INSERT_get_vinsert_imm To.RC:$ins))>;
558558
def : Pat<(Cast.VT
@@ -562,7 +562,7 @@ let Predicates = p in {
562562
(From.VT (From.LdFrag addr:$src2)),
563563
(iPTR imm))),
564564
Cast.ImmAllZerosV)),
565-
(!cast<Instruction>(InstrStr#"rmkz")
565+
(!cast<Instruction>(InstrStr#"rmikz")
566566
Cast.KRCWM:$mask, To.RC:$src1, addr:$src2,
567567
(INSERT_get_vinsert_imm To.RC:$ins))>;
568568
}
@@ -677,15 +677,15 @@ multiclass vextract_for_size_split<int Opcode,
677677
SchedWrite SchedRR, SchedWrite SchedMR> {
678678

679679
let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
680-
defm rr : AVX512_maskable_split<Opcode, MRMDestReg, To, (outs To.RC:$dst),
680+
defm rri : AVX512_maskable_split<Opcode, MRMDestReg, To, (outs To.RC:$dst),
681681
(ins From.RC:$src1, u8imm:$idx),
682682
"vextract" # To.EltTypeName # "x" # To.NumElts,
683683
"$idx, $src1", "$src1, $idx",
684684
(vextract_extract:$idx (From.VT From.RC:$src1), (iPTR imm)),
685685
(vextract_for_mask:$idx (From.VT From.RC:$src1), (iPTR imm))>,
686686
AVX512AIi8Base, EVEX, Sched<[SchedRR]>;
687687

688-
def mr : AVX512AIi8<Opcode, MRMDestMem, (outs),
688+
def mri : AVX512AIi8<Opcode, MRMDestMem, (outs),
689689
(ins To.MemOp:$dst, From.RC:$src1, u8imm:$idx),
690690
"vextract" # To.EltTypeName # "x" # To.NumElts #
691691
"\t{$idx, $src1, $dst|$dst, $src1, $idx}",
@@ -695,7 +695,7 @@ multiclass vextract_for_size_split<int Opcode,
695695
Sched<[SchedMR]>;
696696

697697
let mayStore = 1, hasSideEffects = 0 in
698-
def mrk : AVX512AIi8<Opcode, MRMDestMem, (outs),
698+
def mrik : AVX512AIi8<Opcode, MRMDestMem, (outs),
699699
(ins To.MemOp:$dst, To.KRCWM:$mask,
700700
From.RC:$src1, u8imm:$idx),
701701
"vextract" # To.EltTypeName # "x" # To.NumElts #
@@ -718,12 +718,12 @@ multiclass vextract_for_size_lowering<string InstrStr, X86VectorVTInfo From,
718718
SDNodeXForm EXTRACT_get_vextract_imm, list<Predicate> p> {
719719
let Predicates = p in {
720720
def : Pat<(vextract_extract:$ext (From.VT From.RC:$src1), (iPTR imm)),
721-
(To.VT (!cast<Instruction>(InstrStr#"rr")
721+
(To.VT (!cast<Instruction>(InstrStr#"rri")
722722
From.RC:$src1,
723723
(EXTRACT_get_vextract_imm To.RC:$ext)))>;
724724
def : Pat<(store (To.VT (vextract_extract:$ext (From.VT From.RC:$src1),
725725
(iPTR imm))), addr:$dst),
726-
(!cast<Instruction>(InstrStr#"mr") addr:$dst, From.RC:$src1,
726+
(!cast<Instruction>(InstrStr#"mri") addr:$dst, From.RC:$src1,
727727
(EXTRACT_get_vextract_imm To.RC:$ext))>;
728728
}
729729
}
@@ -828,31 +828,31 @@ defm : vextract_for_size_lowering<"VEXTRACTF64x4Z", v32bf16_info, v16bf16x_info,
828828
// smaller extract to enable EVEX->VEX.
829829
let Predicates = [NoVLX, HasEVEX512] in {
830830
def : Pat<(v2i64 (extract_subvector (v8i64 VR512:$src), (iPTR 2))),
831-
(v2i64 (VEXTRACTI128rr
831+
(v2i64 (VEXTRACTI128rri
832832
(v4i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_ymm)),
833833
(iPTR 1)))>;
834834
def : Pat<(v2f64 (extract_subvector (v8f64 VR512:$src), (iPTR 2))),
835-
(v2f64 (VEXTRACTF128rr
835+
(v2f64 (VEXTRACTF128rri
836836
(v4f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_ymm)),
837837
(iPTR 1)))>;
838838
def : Pat<(v4i32 (extract_subvector (v16i32 VR512:$src), (iPTR 4))),
839-
(v4i32 (VEXTRACTI128rr
839+
(v4i32 (VEXTRACTI128rri
840840
(v8i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_ymm)),
841841
(iPTR 1)))>;
842842
def : Pat<(v4f32 (extract_subvector (v16f32 VR512:$src), (iPTR 4))),
843-
(v4f32 (VEXTRACTF128rr
843+
(v4f32 (VEXTRACTF128rri
844844
(v8f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_ymm)),
845845
(iPTR 1)))>;
846846
def : Pat<(v8i16 (extract_subvector (v32i16 VR512:$src), (iPTR 8))),
847-
(v8i16 (VEXTRACTI128rr
847+
(v8i16 (VEXTRACTI128rri
848848
(v16i16 (EXTRACT_SUBREG (v32i16 VR512:$src), sub_ymm)),
849849
(iPTR 1)))>;
850850
def : Pat<(v8f16 (extract_subvector (v32f16 VR512:$src), (iPTR 8))),
851-
(v8f16 (VEXTRACTF128rr
851+
(v8f16 (VEXTRACTF128rri
852852
(v16f16 (EXTRACT_SUBREG (v32f16 VR512:$src), sub_ymm)),
853853
(iPTR 1)))>;
854854
def : Pat<(v16i8 (extract_subvector (v64i8 VR512:$src), (iPTR 16))),
855-
(v16i8 (VEXTRACTI128rr
855+
(v16i8 (VEXTRACTI128rri
856856
(v32i8 (EXTRACT_SUBREG (v64i8 VR512:$src), sub_ymm)),
857857
(iPTR 1)))>;
858858
}
@@ -861,31 +861,31 @@ def : Pat<(v16i8 (extract_subvector (v64i8 VR512:$src), (iPTR 16))),
861861
// smaller extract to enable EVEX->VEX.
862862
let Predicates = [HasVLX] in {
863863
def : Pat<(v2i64 (extract_subvector (v8i64 VR512:$src), (iPTR 2))),
864-
(v2i64 (VEXTRACTI32x4Z256rr
864+
(v2i64 (VEXTRACTI32x4Z256rri
865865
(v4i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_ymm)),
866866
(iPTR 1)))>;
867867
def : Pat<(v2f64 (extract_subvector (v8f64 VR512:$src), (iPTR 2))),
868-
(v2f64 (VEXTRACTF32x4Z256rr
868+
(v2f64 (VEXTRACTF32x4Z256rri
869869
(v4f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_ymm)),
870870
(iPTR 1)))>;
871871
def : Pat<(v4i32 (extract_subvector (v16i32 VR512:$src), (iPTR 4))),
872-
(v4i32 (VEXTRACTI32x4Z256rr
872+
(v4i32 (VEXTRACTI32x4Z256rri
873873
(v8i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_ymm)),
874874
(iPTR 1)))>;
875875
def : Pat<(v4f32 (extract_subvector (v16f32 VR512:$src), (iPTR 4))),
876-
(v4f32 (VEXTRACTF32x4Z256rr
876+
(v4f32 (VEXTRACTF32x4Z256rri
877877
(v8f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_ymm)),
878878
(iPTR 1)))>;
879879
def : Pat<(v8i16 (extract_subvector (v32i16 VR512:$src), (iPTR 8))),
880-
(v8i16 (VEXTRACTI32x4Z256rr
880+
(v8i16 (VEXTRACTI32x4Z256rri
881881
(v16i16 (EXTRACT_SUBREG (v32i16 VR512:$src), sub_ymm)),
882882
(iPTR 1)))>;
883883
def : Pat<(v8f16 (extract_subvector (v32f16 VR512:$src), (iPTR 8))),
884-
(v8f16 (VEXTRACTF32x4Z256rr
884+
(v8f16 (VEXTRACTF32x4Z256rri
885885
(v16f16 (EXTRACT_SUBREG (v32f16 VR512:$src), sub_ymm)),
886886
(iPTR 1)))>;
887887
def : Pat<(v16i8 (extract_subvector (v64i8 VR512:$src), (iPTR 16))),
888-
(v16i8 (VEXTRACTI32x4Z256rr
888+
(v16i8 (VEXTRACTI32x4Z256rri
889889
(v32i8 (EXTRACT_SUBREG (v64i8 VR512:$src), sub_ymm)),
890890
(iPTR 1)))>;
891891
}
@@ -904,7 +904,7 @@ let Predicates = p in {
904904
(To.VT (vextract_extract:$ext
905905
(From.VT From.RC:$src), (iPTR imm)))),
906906
To.RC:$src0)),
907-
(Cast.VT (!cast<Instruction>(InstrStr#"rrk")
907+
(Cast.VT (!cast<Instruction>(InstrStr#"rrik")
908908
Cast.RC:$src0, Cast.KRCWM:$mask, From.RC:$src,
909909
(EXTRACT_get_vextract_imm To.RC:$ext)))>;
910910

@@ -913,7 +913,7 @@ let Predicates = p in {
913913
(To.VT (vextract_extract:$ext
914914
(From.VT From.RC:$src), (iPTR imm)))),
915915
Cast.ImmAllZerosV)),
916-
(Cast.VT (!cast<Instruction>(InstrStr#"rrkz")
916+
(Cast.VT (!cast<Instruction>(InstrStr#"rrikz")
917917
Cast.KRCWM:$mask, From.RC:$src,
918918
(EXTRACT_get_vextract_imm To.RC:$ext)))>;
919919
}

‎llvm/lib/Target/X86/X86InstrInfo.cpp‎

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -2597,8 +2597,8 @@ MachineInstr *X86InstrInfo::commuteInstructionImpl(MachineInstr &MI, bool NewMI,
25972597
.setImm(X86::getSwappedVCMPImm(
25982598
MI.getOperand(MI.getNumExplicitOperands() - 1).getImm() & 0x1f));
25992599
break;
2600-
case X86::VPERM2F128rr:
2601-
case X86::VPERM2I128rr:
2600+
case X86::VPERM2F128rri:
2601+
case X86::VPERM2I128rri:
26022602
// Flip permute source immediate.
26032603
// Imm & 0x02: lo = if set, select Op1.lo/hi else Op0.lo/hi.
26042604
// Imm & 0x20: hi = if set, select Op1.lo/hi else Op0.lo/hi.
@@ -6258,16 +6258,16 @@ bool X86InstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
62586258
get(X86::VBROADCASTF64X4rm), X86::sub_ymm);
62596259
case X86::VMOVAPSZ128mr_NOVLX:
62606260
return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVAPSmr),
6261-
get(X86::VEXTRACTF32x4Zmr), X86::sub_xmm);
6261+
get(X86::VEXTRACTF32x4Zmri), X86::sub_xmm);
62626262
case X86::VMOVUPSZ128mr_NOVLX:
62636263
return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVUPSmr),
6264-
get(X86::VEXTRACTF32x4Zmr), X86::sub_xmm);
6264+
get(X86::VEXTRACTF32x4Zmri), X86::sub_xmm);
62656265
case X86::VMOVAPSZ256mr_NOVLX:
62666266
return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVAPSYmr),
6267-
get(X86::VEXTRACTF64x4Zmr), X86::sub_ymm);
6267+
get(X86::VEXTRACTF64x4Zmri), X86::sub_ymm);
62686268
case X86::VMOVUPSZ256mr_NOVLX:
62696269
return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVUPSYmr),
6270-
get(X86::VEXTRACTF64x4Zmr), X86::sub_ymm);
6270+
get(X86::VEXTRACTF64x4Zmri), X86::sub_ymm);
62716271
case X86::MOV32ri64: {
62726272
Register Reg = MIB.getReg(0);
62736273
Register Reg32 = RI.getSubReg(Reg, X86::sub_32bit);
@@ -6775,8 +6775,8 @@ static bool hasUndefRegUpdate(unsigned Opcode, unsigned OpNum,
67756775
case X86::VPACKUSWBZ128rr:
67766776
case X86::VPACKSSDWZ128rr:
67776777
case X86::VPACKUSDWZ128rr:
6778-
case X86::VPERM2F128rr:
6779-
case X86::VPERM2I128rr:
6778+
case X86::VPERM2F128rri:
6779+
case X86::VPERM2I128rri:
67806780
case X86::VSHUFF32X4Z256rri:
67816781
case X86::VSHUFF32X4Zrri:
67826782
case X86::VSHUFF64X2Z256rri:

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