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[RISCV] Add Qualcomm uC Xqcia (Arithmetic) extension (llvm#118113)
This extension adds 11 instructions that perform integer arithmetic. The current spec can be found at: https://github.com/quic/riscv-unified-db/releases/latest This patch adds assembler only support.
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‎clang/test/Driver/print-supported-extensions-riscv.c‎

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@@ -188,6 +188,7 @@
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// CHECK-NEXT: smctr 1.0 'Smctr' (Control Transfer Records Machine Level)
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// CHECK-NEXT: ssctr 1.0 'Ssctr' (Control Transfer Records Supervisor Level)
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// CHECK-NEXT: svukte 0.3 'Svukte' (Address-Independent Latency of User-Mode Faults to Supervisor Addresses)
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// CHECK-NEXT: xqcia 0.2 'Xqcia' (Qualcomm uC Arithmetic Extension)
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// CHECK-NEXT: xqcicsr 0.2 'Xqcicsr' (Qualcomm uC CSR Extension)
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// CHECK-NEXT: xqcisls 0.2 'Xqcisls' (Qualcomm uC Scaled Load Store Extension)
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// CHECK-EMPTY:

‎llvm/docs/RISCVUsage.rst‎

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@@ -426,6 +426,9 @@ The current vendor extensions supported are:
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``Xwchc``
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LLVM implements `the custom compressed opcodes present in some QingKe cores` by WCH / Nanjing Qinheng Microelectronics. The vendor refers to these opcodes by the name "XW".
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``experimental-Xqcia``
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LLVM implements `version 0.2 of the Qualcomm uC Arithmetic extension specification <https://github.com/quic/riscv-unified-db/releases/latest>`__ by Qualcomm. All instructions are prefixed with `qc.` as described in the specification. These instructions are only available for riscv32.
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``experimental-Xqcicsr``
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LLVM implements `version 0.2 of the Qualcomm uC CSR extension specification <https://github.com/quic/riscv-unified-db/releases/latest>`__ by Qualcomm. All instructions are prefixed with `qc.` as described in the specification. These instructions are only available for riscv32.
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‎llvm/docs/ReleaseNotes.md‎

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@@ -215,6 +215,8 @@ Changes to the RISC-V Backend
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extension.
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* Adds experimental assembler support for the Qualcomm uC 'Xqcisls` (Scaled Load Store)
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extension.
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* Adds experimental assembler support for the Qualcomm uC 'Xqcia` (Arithmetic)
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extension.
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Changes to the WebAssembly Backend
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----------------------------------

‎llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp‎

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@@ -717,6 +717,7 @@ struct RISCVOperand final : public MCParsedAsmOperand {
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bool isUImm6() const { return IsUImm<6>(); }
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bool isUImm7() const { return IsUImm<7>(); }
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bool isUImm8() const { return IsUImm<8>(); }
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bool isUImm11() const { return IsUImm<11>(); }
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bool isUImm16() const { return IsUImm<16>(); }
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bool isUImm20() const { return IsUImm<20>(); }
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bool isUImm32() const { return IsUImm<32>(); }
@@ -1563,6 +1564,8 @@ bool RISCVAsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
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return generateImmOutOfRangeError(
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Operands, ErrorInfo, -(1 << 9), (1 << 9) - 16,
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"immediate must be a multiple of 16 bytes and non-zero in the range");
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case Match_InvalidUImm11:
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return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 11) - 1);
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case Match_InvalidSImm12:
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return generateImmOutOfRangeError(
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Operands, ErrorInfo, -(1 << 11), (1 << 11) - 1,

‎llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp‎

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@@ -686,6 +686,8 @@ DecodeStatus RISCVDisassembler::getInstruction32(MCInst &MI, uint64_t &Size,
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"Qualcomm uC CSR custom opcode table");
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TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXqcisls, DecoderTableXqcisls32,
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"Qualcomm uC Scaled Load Store custom opcode table");
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TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXqcia, DecoderTableXqcia32,
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"Qualcomm uC Arithmetic custom opcode table");
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TRY_TO_DECODE(true, DecoderTable32, "RISCV32 table");
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return MCDisassembler::Fail;

‎llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h‎

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@@ -312,6 +312,7 @@ enum OperandType : unsigned {
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OPERAND_UIMM8_GE32,
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OPERAND_UIMM9_LSB000,
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OPERAND_UIMM10_LSB00_NONZERO,
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OPERAND_UIMM11,
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OPERAND_UIMM12,
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OPERAND_UIMM16,
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OPERAND_UIMM32,

‎llvm/lib/Target/RISCV/RISCVFeatures.td‎

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@@ -1359,6 +1359,14 @@ def HasVendorXqcisls
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AssemblerPredicate<(all_of FeatureVendorXqcisls),
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"'Xqcisls' (Qualcomm uC Scaled Load Store Extension)">;
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def FeatureVendorXqcia
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: RISCVExperimentalExtension<"xqcia", 0, 2,
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"'Xqcia' (Qualcomm uC Arithmetic Extension)">;
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def HasVendorXqcia
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: Predicate<"Subtarget->hasVendorXqcia()">,
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AssemblerPredicate<(all_of FeatureVendorXqcia),
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"'Xqcia' (Qualcomm uC Arithmetic Extension)">;
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//===----------------------------------------------------------------------===//
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// LLVM specific features and extensions
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//===----------------------------------------------------------------------===//

‎llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td‎

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@@ -14,6 +14,8 @@
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// Operand and SDNode transformation definitions.
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//===----------------------------------------------------------------------===//
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def uimm11 : RISCVUImmLeafOp<11>;
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//===----------------------------------------------------------------------===//
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// Instruction Formats
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//===----------------------------------------------------------------------===//
@@ -45,6 +47,16 @@ class QCIStore_ScaleIdx<bits<4> func4, string opcodestr>
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}
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}
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class QCIRVInstR<bits<4> func4, string opcodestr>
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: RVInstR<{0b000, func4}, 0b011, OPC_CUSTOM_0, (outs GPRNoX0:$rd),
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(ins GPRNoX0:$rs1), opcodestr, "$rd, $rs1"> {
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let rs2 = 0;
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}
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class QCIRVInstRR<bits<5> func5, DAGOperand InTyRs1, string opcodestr>
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: RVInstR<{0b00, func5}, 0b011, OPC_CUSTOM_0, (outs GPRNoX0:$rd),
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(ins InTyRs1:$rs1, GPRNoX0:$rs2), opcodestr, "$rd, $rs1, $rs2">;
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//===----------------------------------------------------------------------===//
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// Instructions
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//===----------------------------------------------------------------------===//
@@ -72,3 +84,27 @@ let Predicates = [HasVendorXqcisls, IsRV32], DecoderNamespace = "Xqcisls" in {
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def QC_SRH : QCIStore_ScaleIdx<0b1110, "qc.srh">;
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def QC_SRW : QCIStore_ScaleIdx<0b1111, "qc.srw">;
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} // Predicates = [HasVendorXqcisls, IsRV32], DecoderNamespace = "Xqcisls"
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let Predicates = [HasVendorXqcia, IsRV32], DecoderNamespace = "Xqcia" in {
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let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
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def QC_SLASAT : QCIRVInstRR<0b01010, GPRNoX0, "qc.slasat">;
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def QC_SLLSAT : QCIRVInstRR<0b01100, GPRNoX0, "qc.sllsat">;
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def QC_ADDSAT : QCIRVInstRR<0b01110, GPRNoX0, "qc.addsat">;
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def QC_ADDUSAT : QCIRVInstRR<0b01111, GPRNoX0, "qc.addusat">;
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def QC_SUBSAT : QCIRVInstRR<0b10000, GPRNoX0, "qc.subsat">;
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def QC_SUBUSAT : QCIRVInstRR<0b10001, GPRNoX0, "qc.subusat">;
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def QC_WRAP : QCIRVInstRR<0b10010, GPR, "qc.wrap">;
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def QC_WRAPI : RVInstI<0b000, OPC_CUSTOM_0, (outs GPRNoX0:$rd),
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(ins GPRNoX0:$rs1, uimm11:$imm11), "qc.wrapi",
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"$rd, $rs1, $imm11"> {
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bits<11> imm11;
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let imm12 = {0b0, imm11};
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}
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def QC_NORM : QCIRVInstR<0b0111, "qc.norm">;
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def QC_NORMU : QCIRVInstR<0b1000, "qc.normu">;
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def QC_NORMEU : QCIRVInstR<0b1001, "qc.normeu">;
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} // hasSideEffects = 0, mayLoad = 0, mayStore = 0
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} // Predicates = [HasVendorXqcia, IsRV32], DecoderNamespace = "Xqcia"

‎llvm/lib/TargetParser/RISCVISAInfo.cpp‎

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@@ -741,7 +741,8 @@ Error RISCVISAInfo::checkDependency() {
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bool HasVector = Exts.count("zve32x") != 0;
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bool HasZvl = MinVLen != 0;
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bool HasZcmt = Exts.count("zcmt") != 0;
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static constexpr StringLiteral XqciExts[] = {{"xqcicsr"}, {"xqcisls"}};
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static constexpr StringLiteral XqciExts[] = {
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{"xqcia"}, {"xqcicsr"}, {"xqcisls"}};
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if (HasI && HasE)
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return getIncompatibleError("i", "e");

‎llvm/test/CodeGen/RISCV/attributes.ll‎

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@@ -81,6 +81,7 @@
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; RUN: llc -mtriple=riscv32 -mattr=+xtheadmempair %s -o - | FileCheck --check-prefix=RV32XTHEADMEMPAIR %s
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; RUN: llc -mtriple=riscv32 -mattr=+xtheadsync %s -o - | FileCheck --check-prefix=RV32XTHEADSYNC %s
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; RUN: llc -mtriple=riscv32 -mattr=+xwchc %s -o - | FileCheck --check-prefix=RV32XWCHC %s
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcia %s -o - | FileCheck --check-prefix=RV32XQCIA %s
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcicsr %s -o - | FileCheck --check-prefix=RV32XQCICSR %s
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcisls %s -o - | FileCheck --check-prefix=RV32XQCISLS %s
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; RUN: llc -mtriple=riscv32 -mattr=+zaamo %s -o - | FileCheck --check-prefix=RV32ZAAMO %s
@@ -387,6 +388,7 @@
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; RV32XTHEADMEMPAIR: .attribute 5, "rv32i2p1_xtheadmempair1p0"
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; RV32XTHEADSYNC: .attribute 5, "rv32i2p1_xtheadsync1p0"
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; RV32XWCHC: .attribute 5, "rv32i2p1_xwchc2p2"
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; RV32XQCIA: .attribute 5, "rv32i2p1_xqcia0p2"
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; RV32XQCICSR: .attribute 5, "rv32i2p1_xqcicsr0p2"
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; RV32XQCISLS: .attribute 5, "rv32i2p1_xqcisls0p2"
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; RV32ZAAMO: .attribute 5, "rv32i2p1_zaamo1p0"

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