Skip to content

Commit 68ed172

Browse files
fhahnfhahn
committed
[VPlan] Unify mayWriteToMemory and mayHaveSideEffects logic for VPInst.
Unify logic for mayWriteToMemory and mayHaveSideEffects for VPInstruction, with the later relying on the former. Also extend to handle binary operators. Split off from llvm#106441
1 parent 8336819 commit 68ed172

File tree

4 files changed

+25
-42
lines changed

4 files changed

+25
-42
lines changed

‎llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp‎

Lines changed: 19 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -48,6 +48,24 @@ extern cl::opt<unsigned> ForceTargetInstructionCost;
4848

4949
bool VPRecipeBase::mayWriteToMemory() const {
5050
switch (getVPDefID()) {
51+
case VPInstructionSC:
52+
if (Instruction::isBinaryOp(cast<VPInstruction>(this)->getOpcode()))
53+
return false;
54+
switch (cast<VPInstruction>(this)->getOpcode()) {
55+
case Instruction::Or:
56+
case Instruction::ICmp:
57+
case Instruction::Select:
58+
case VPInstruction::Not:
59+
case VPInstruction::CalculateTripCountMinusVF:
60+
case VPInstruction::CanonicalIVIncrementForPart:
61+
case VPInstruction::ExtractFromEnd:
62+
case VPInstruction::FirstOrderRecurrenceSplice:
63+
case VPInstruction::LogicalAnd:
64+
case VPInstruction::PtrAdd:
65+
return false;
66+
default:
67+
return true;
68+
}
5169
case VPInterleaveSC:
5270
return cast<VPInterleaveRecipe>(this)->getNumStoreOperands() > 0;
5371
case VPWidenStoreEVLSC:
@@ -137,21 +155,7 @@ bool VPRecipeBase::mayHaveSideEffects() const {
137155
case VPScalarCastSC:
138156
return false;
139157
case VPInstructionSC:
140-
switch (cast<VPInstruction>(this)->getOpcode()) {
141-
case Instruction::Or:
142-
case Instruction::ICmp:
143-
case Instruction::Select:
144-
case VPInstruction::Not:
145-
case VPInstruction::CalculateTripCountMinusVF:
146-
case VPInstruction::CanonicalIVIncrementForPart:
147-
case VPInstruction::ExtractFromEnd:
148-
case VPInstruction::FirstOrderRecurrenceSplice:
149-
case VPInstruction::LogicalAnd:
150-
case VPInstruction::PtrAdd:
151-
return false;
152-
default:
153-
return true;
154-
}
158+
return mayWriteToMemory();
155159
case VPWidenCallSC: {
156160
Function *Fn = cast<VPWidenCallRecipe>(this)->getCalledScalarFunction();
157161
return mayWriteToMemory() || !Fn->doesNotThrow() || !Fn->willReturn();

‎llvm/test/Transforms/LoopVectorize/X86/iv-live-outs.ll‎

Lines changed: 0 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -17,13 +17,7 @@ define i64 @test_pr98660(ptr %dst, i64 %N) {
1717
; CHECK: [[VECTOR_BODY]]:
1818
; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
1919
; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[INDEX]], 0
20-
; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[INDEX]], 8
21-
; CHECK-NEXT: [[TMP3:%.*]] = add i64 [[INDEX]], 16
22-
; CHECK-NEXT: [[TMP4:%.*]] = add i64 [[INDEX]], 24
2320
; CHECK-NEXT: [[TMP5:%.*]] = add i64 [[TMP1]], 1
24-
; CHECK-NEXT: [[TMP6:%.*]] = add i64 [[TMP2]], 1
25-
; CHECK-NEXT: [[TMP7:%.*]] = add i64 [[TMP3]], 1
26-
; CHECK-NEXT: [[TMP8:%.*]] = add i64 [[TMP4]], 1
2721
; CHECK-NEXT: [[TMP9:%.*]] = getelementptr i32, ptr [[DST]], i64 [[TMP5]]
2822
; CHECK-NEXT: [[TMP13:%.*]] = getelementptr i32, ptr [[TMP9]], i32 0
2923
; CHECK-NEXT: [[TMP14:%.*]] = getelementptr i32, ptr [[TMP9]], i32 8

‎llvm/test/Transforms/LoopVectorize/X86/widened-value-used-as-scalar-and-first-lane.ll‎

Lines changed: 4 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -35,15 +35,9 @@ define void @iv.4_used_as_vector_and_first_lane(ptr %src, ptr noalias %dst) {
3535
; CHECK-NEXT: [[TMP17:%.*]] = icmp ule <4 x i64> [[WIDE_LOAD4]], <i64 128, i64 128, i64 128, i64 128>
3636
; CHECK-NEXT: [[TMP18:%.*]] = icmp ule <4 x i64> [[WIDE_LOAD5]], <i64 128, i64 128, i64 128, i64 128>
3737
; CHECK-NEXT: [[TMP19:%.*]] = icmp ule <4 x i64> [[WIDE_LOAD6]], <i64 128, i64 128, i64 128, i64 128>
38-
; CHECK-NEXT: [[TMP20:%.*]] = extractelement <4 x i64> [[TMP12]], i32 0
39-
; CHECK-NEXT: [[TMP21:%.*]] = add i64 [[TMP20]], 1
40-
; CHECK-NEXT: [[TMP22:%.*]] = extractelement <4 x i64> [[TMP13]], i32 0
41-
; CHECK-NEXT: [[TMP23:%.*]] = add i64 [[TMP22]], 1
42-
; CHECK-NEXT: [[TMP24:%.*]] = extractelement <4 x i64> [[TMP14]], i32 0
43-
; CHECK-NEXT: [[TMP25:%.*]] = add i64 [[TMP24]], 1
44-
; CHECK-NEXT: [[TMP26:%.*]] = extractelement <4 x i64> [[TMP15]], i32 0
38+
; CHECK-NEXT: [[TMP26:%.*]] = extractelement <4 x i64> [[TMP12]], i32 0
4539
; CHECK-NEXT: [[TMP27:%.*]] = add i64 [[TMP26]], 1
46-
; CHECK-NEXT: [[TMP28:%.*]] = getelementptr i64, ptr [[DST]], i64 [[TMP21]]
40+
; CHECK-NEXT: [[TMP28:%.*]] = getelementptr i64, ptr [[DST]], i64 [[TMP27]]
4741
; CHECK-NEXT: [[TMP32:%.*]] = getelementptr i64, ptr [[TMP28]], i32 0
4842
; CHECK-NEXT: [[TMP33:%.*]] = getelementptr i64, ptr [[TMP28]], i32 4
4943
; CHECK-NEXT: [[TMP34:%.*]] = getelementptr i64, ptr [[TMP28]], i32 8
@@ -116,9 +110,6 @@ define void @iv.4_used_as_first_lane(ptr %src, ptr noalias %dst) {
116110
; CHECK: vector.body:
117111
; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
118112
; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 0
119-
; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[INDEX]], 4
120-
; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[INDEX]], 8
121-
; CHECK-NEXT: [[TMP3:%.*]] = add i64 [[INDEX]], 12
122113
; CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[SRC]], i64 [[TMP0]]
123114
; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds i64, ptr [[TMP4]], i32 0
124115
; CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds i64, ptr [[TMP4]], i32 4
@@ -128,19 +119,13 @@ define void @iv.4_used_as_first_lane(ptr %src, ptr noalias %dst) {
128119
; CHECK-NEXT: [[WIDE_LOAD1:%.*]] = load <4 x i64>, ptr [[TMP9]], align 8
129120
; CHECK-NEXT: [[WIDE_LOAD2:%.*]] = load <4 x i64>, ptr [[TMP10]], align 8
130121
; CHECK-NEXT: [[WIDE_LOAD3:%.*]] = load <4 x i64>, ptr [[TMP11]], align 8
131-
; CHECK-NEXT: [[TMP12:%.*]] = add i64 [[TMP0]], 4
132-
; CHECK-NEXT: [[TMP13:%.*]] = add i64 [[TMP1]], 4
133-
; CHECK-NEXT: [[TMP14:%.*]] = add i64 [[TMP2]], 4
134-
; CHECK-NEXT: [[TMP15:%.*]] = add i64 [[TMP3]], 4
122+
; CHECK-NEXT: [[TMP15:%.*]] = add i64 [[TMP0]], 4
135123
; CHECK-NEXT: [[TMP16:%.*]] = icmp ule <4 x i64> [[WIDE_LOAD]], <i64 128, i64 128, i64 128, i64 128>
136124
; CHECK-NEXT: [[TMP17:%.*]] = icmp ule <4 x i64> [[WIDE_LOAD1]], <i64 128, i64 128, i64 128, i64 128>
137125
; CHECK-NEXT: [[TMP18:%.*]] = icmp ule <4 x i64> [[WIDE_LOAD2]], <i64 128, i64 128, i64 128, i64 128>
138126
; CHECK-NEXT: [[TMP19:%.*]] = icmp ule <4 x i64> [[WIDE_LOAD3]], <i64 128, i64 128, i64 128, i64 128>
139-
; CHECK-NEXT: [[TMP20:%.*]] = add i64 [[TMP12]], 1
140-
; CHECK-NEXT: [[TMP21:%.*]] = add i64 [[TMP13]], 1
141-
; CHECK-NEXT: [[TMP22:%.*]] = add i64 [[TMP14]], 1
142127
; CHECK-NEXT: [[TMP23:%.*]] = add i64 [[TMP15]], 1
143-
; CHECK-NEXT: [[TMP24:%.*]] = getelementptr i64, ptr [[DST]], i64 [[TMP20]]
128+
; CHECK-NEXT: [[TMP24:%.*]] = getelementptr i64, ptr [[DST]], i64 [[TMP23]]
144129
; CHECK-NEXT: [[TMP28:%.*]] = getelementptr i64, ptr [[TMP24]], i32 0
145130
; CHECK-NEXT: [[TMP29:%.*]] = getelementptr i64, ptr [[TMP24]], i32 4
146131
; CHECK-NEXT: [[TMP30:%.*]] = getelementptr i64, ptr [[TMP24]], i32 8

‎llvm/unittests/Transforms/Vectorize/VPlanTest.cpp‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1230,9 +1230,9 @@ TEST(VPRecipeTest, MayHaveSideEffectsAndMayReadWriteMemory) {
12301230
VPValue Op2;
12311231
VPInstruction VPInst(Instruction::Add, {&Op1, &Op2});
12321232
VPRecipeBase &Recipe = VPInst;
1233-
EXPECT_TRUE(Recipe.mayHaveSideEffects());
1233+
EXPECT_FALSE(Recipe.mayHaveSideEffects());
12341234
EXPECT_TRUE(Recipe.mayReadFromMemory());
1235-
EXPECT_TRUE(Recipe.mayWriteToMemory());
1235+
EXPECT_FALSE(Recipe.mayWriteToMemory());
12361236
EXPECT_TRUE(Recipe.mayReadOrWriteMemory());
12371237
}
12381238
{

0 commit comments

Comments
 (0)