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[RISCV] Use FMV.D for moving GPRPairs on RV32_Zdinx (llvm#169556)
This is noted by the specification, and should save a dynamic instruction. Code size should be no worse than before, as the pairs of moves can usually be turned into two 16-bit moves, but `fmv.d` is always a 32-bit instruction. LLVM can look through a `FSGNJ_D_IN32X`, in `RISCVInstrInfo::isCopyInstrImpl` which helps copy propagation.
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6 files changed

+48
-81
lines changed

6 files changed

+48
-81
lines changed

‎llvm/lib/Target/RISCV/RISCVInstrInfo.cpp‎

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -531,6 +531,15 @@ void RISCVInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
531531
}
532532

533533
if (RISCV::GPRPairRegClass.contains(DstReg, SrcReg)) {
534+
if (STI.isRV32() && STI.hasStdExtZdinx()) {
535+
// On RV32_Zdinx, FMV.D will move a pair of registers to another pair of
536+
// registers, in one instruction.
537+
BuildMI(MBB, MBBI, DL, get(RISCV::FSGNJ_D_IN32X), DstReg)
538+
.addReg(SrcReg, getRenamableRegState(RenamableSrc))
539+
.addReg(SrcReg, KillFlag | getRenamableRegState(RenamableSrc));
540+
return;
541+
}
542+
534543
MCRegister EvenReg = TRI->getSubReg(SrcReg, RISCV::sub_gpr_even);
535544
MCRegister OddReg = TRI->getSubReg(SrcReg, RISCV::sub_gpr_odd);
536545
// We need to correct the odd register of X0_Pair.

‎llvm/test/CodeGen/RISCV/double-maximum-minimum.ll‎

Lines changed: 9 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -37,8 +37,7 @@ define double @fminimum_f64(double %a, double %b) nounwind {
3737
; RV32IZFINXZDINX-LABEL: fminimum_f64:
3838
; RV32IZFINXZDINX: # %bb.0:
3939
; RV32IZFINXZDINX-NEXT: feq.d a6, a0, a0
40-
; RV32IZFINXZDINX-NEXT: mv a4, a2
41-
; RV32IZFINXZDINX-NEXT: mv a5, a3
40+
; RV32IZFINXZDINX-NEXT: fmv.d a4, a2
4241
; RV32IZFINXZDINX-NEXT: beqz a6, .LBB0_3
4342
; RV32IZFINXZDINX-NEXT: # %bb.1:
4443
; RV32IZFINXZDINX-NEXT: feq.d a6, a2, a2
@@ -47,14 +46,11 @@ define double @fminimum_f64(double %a, double %b) nounwind {
4746
; RV32IZFINXZDINX-NEXT: fmin.d a0, a0, a4
4847
; RV32IZFINXZDINX-NEXT: ret
4948
; RV32IZFINXZDINX-NEXT: .LBB0_3:
50-
; RV32IZFINXZDINX-NEXT: mv a4, a0
51-
; RV32IZFINXZDINX-NEXT: mv a5, a1
49+
; RV32IZFINXZDINX-NEXT: fmv.d a4, a0
5250
; RV32IZFINXZDINX-NEXT: feq.d a6, a2, a2
5351
; RV32IZFINXZDINX-NEXT: bnez a6, .LBB0_2
5452
; RV32IZFINXZDINX-NEXT: .LBB0_4:
55-
; RV32IZFINXZDINX-NEXT: mv a0, a2
56-
; RV32IZFINXZDINX-NEXT: mv a1, a3
57-
; RV32IZFINXZDINX-NEXT: fmin.d a0, a0, a4
53+
; RV32IZFINXZDINX-NEXT: fmin.d a0, a2, a4
5854
; RV32IZFINXZDINX-NEXT: ret
5955
;
6056
; RV64IZFINXZDINX-LABEL: fminimum_f64:
@@ -104,8 +100,7 @@ define double @fmaximum_f64(double %a, double %b) nounwind {
104100
; RV32IZFINXZDINX-LABEL: fmaximum_f64:
105101
; RV32IZFINXZDINX: # %bb.0:
106102
; RV32IZFINXZDINX-NEXT: feq.d a6, a0, a0
107-
; RV32IZFINXZDINX-NEXT: mv a4, a2
108-
; RV32IZFINXZDINX-NEXT: mv a5, a3
103+
; RV32IZFINXZDINX-NEXT: fmv.d a4, a2
109104
; RV32IZFINXZDINX-NEXT: beqz a6, .LBB1_3
110105
; RV32IZFINXZDINX-NEXT: # %bb.1:
111106
; RV32IZFINXZDINX-NEXT: feq.d a6, a2, a2
@@ -114,14 +109,11 @@ define double @fmaximum_f64(double %a, double %b) nounwind {
114109
; RV32IZFINXZDINX-NEXT: fmax.d a0, a0, a4
115110
; RV32IZFINXZDINX-NEXT: ret
116111
; RV32IZFINXZDINX-NEXT: .LBB1_3:
117-
; RV32IZFINXZDINX-NEXT: mv a4, a0
118-
; RV32IZFINXZDINX-NEXT: mv a5, a1
112+
; RV32IZFINXZDINX-NEXT: fmv.d a4, a0
119113
; RV32IZFINXZDINX-NEXT: feq.d a6, a2, a2
120114
; RV32IZFINXZDINX-NEXT: bnez a6, .LBB1_2
121115
; RV32IZFINXZDINX-NEXT: .LBB1_4:
122-
; RV32IZFINXZDINX-NEXT: mv a0, a2
123-
; RV32IZFINXZDINX-NEXT: mv a1, a3
124-
; RV32IZFINXZDINX-NEXT: fmax.d a0, a0, a4
116+
; RV32IZFINXZDINX-NEXT: fmax.d a0, a2, a4
125117
; RV32IZFINXZDINX-NEXT: ret
126118
;
127119
; RV64IZFINXZDINX-LABEL: fmaximum_f64:
@@ -188,8 +180,7 @@ define double @fmaximum_nnan_f64(double %a, double %b) nounwind {
188180
; RV32IZFINXZDINX-LABEL: fmaximum_nnan_f64:
189181
; RV32IZFINXZDINX: # %bb.0:
190182
; RV32IZFINXZDINX-NEXT: feq.d a6, a0, a0
191-
; RV32IZFINXZDINX-NEXT: mv a4, a2
192-
; RV32IZFINXZDINX-NEXT: mv a5, a3
183+
; RV32IZFINXZDINX-NEXT: fmv.d a4, a2
193184
; RV32IZFINXZDINX-NEXT: beqz a6, .LBB3_3
194185
; RV32IZFINXZDINX-NEXT: # %bb.1:
195186
; RV32IZFINXZDINX-NEXT: feq.d a6, a2, a2
@@ -198,14 +189,11 @@ define double @fmaximum_nnan_f64(double %a, double %b) nounwind {
198189
; RV32IZFINXZDINX-NEXT: fmin.d a0, a0, a4
199190
; RV32IZFINXZDINX-NEXT: ret
200191
; RV32IZFINXZDINX-NEXT: .LBB3_3:
201-
; RV32IZFINXZDINX-NEXT: mv a4, a0
202-
; RV32IZFINXZDINX-NEXT: mv a5, a1
192+
; RV32IZFINXZDINX-NEXT: fmv.d a4, a0
203193
; RV32IZFINXZDINX-NEXT: feq.d a6, a2, a2
204194
; RV32IZFINXZDINX-NEXT: bnez a6, .LBB3_2
205195
; RV32IZFINXZDINX-NEXT: .LBB3_4:
206-
; RV32IZFINXZDINX-NEXT: mv a0, a2
207-
; RV32IZFINXZDINX-NEXT: mv a1, a3
208-
; RV32IZFINXZDINX-NEXT: fmin.d a0, a0, a4
196+
; RV32IZFINXZDINX-NEXT: fmin.d a0, a2, a4
209197
; RV32IZFINXZDINX-NEXT: ret
210198
;
211199
; RV64IZFINXZDINX-LABEL: fmaximum_nnan_f64:

‎llvm/test/CodeGen/RISCV/double-select-fcmp.ll‎

Lines changed: 16 additions & 32 deletions
Original file line numberDiff line numberDiff line change
@@ -44,8 +44,7 @@ define double @select_fcmp_oeq(double %a, double %b) nounwind {
4444
; CHECKRV32ZDINX-NEXT: feq.d a4, a0, a2
4545
; CHECKRV32ZDINX-NEXT: bnez a4, .LBB1_2
4646
; CHECKRV32ZDINX-NEXT: # %bb.1:
47-
; CHECKRV32ZDINX-NEXT: mv a0, a2
48-
; CHECKRV32ZDINX-NEXT: mv a1, a3
47+
; CHECKRV32ZDINX-NEXT: fmv.d a0, a2
4948
; CHECKRV32ZDINX-NEXT: .LBB1_2:
5049
; CHECKRV32ZDINX-NEXT: ret
5150
;
@@ -77,8 +76,7 @@ define double @select_fcmp_ogt(double %a, double %b) nounwind {
7776
; CHECKRV32ZDINX-NEXT: flt.d a4, a2, a0
7877
; CHECKRV32ZDINX-NEXT: bnez a4, .LBB2_2
7978
; CHECKRV32ZDINX-NEXT: # %bb.1:
80-
; CHECKRV32ZDINX-NEXT: mv a0, a2
81-
; CHECKRV32ZDINX-NEXT: mv a1, a3
79+
; CHECKRV32ZDINX-NEXT: fmv.d a0, a2
8280
; CHECKRV32ZDINX-NEXT: .LBB2_2:
8381
; CHECKRV32ZDINX-NEXT: ret
8482
;
@@ -110,8 +108,7 @@ define double @select_fcmp_oge(double %a, double %b) nounwind {
110108
; CHECKRV32ZDINX-NEXT: fle.d a4, a2, a0
111109
; CHECKRV32ZDINX-NEXT: bnez a4, .LBB3_2
112110
; CHECKRV32ZDINX-NEXT: # %bb.1:
113-
; CHECKRV32ZDINX-NEXT: mv a0, a2
114-
; CHECKRV32ZDINX-NEXT: mv a1, a3
111+
; CHECKRV32ZDINX-NEXT: fmv.d a0, a2
115112
; CHECKRV32ZDINX-NEXT: .LBB3_2:
116113
; CHECKRV32ZDINX-NEXT: ret
117114
;
@@ -143,8 +140,7 @@ define double @select_fcmp_olt(double %a, double %b) nounwind {
143140
; CHECKRV32ZDINX-NEXT: flt.d a4, a0, a2
144141
; CHECKRV32ZDINX-NEXT: bnez a4, .LBB4_2
145142
; CHECKRV32ZDINX-NEXT: # %bb.1:
146-
; CHECKRV32ZDINX-NEXT: mv a0, a2
147-
; CHECKRV32ZDINX-NEXT: mv a1, a3
143+
; CHECKRV32ZDINX-NEXT: fmv.d a0, a2
148144
; CHECKRV32ZDINX-NEXT: .LBB4_2:
149145
; CHECKRV32ZDINX-NEXT: ret
150146
;
@@ -176,8 +172,7 @@ define double @select_fcmp_ole(double %a, double %b) nounwind {
176172
; CHECKRV32ZDINX-NEXT: fle.d a4, a0, a2
177173
; CHECKRV32ZDINX-NEXT: bnez a4, .LBB5_2
178174
; CHECKRV32ZDINX-NEXT: # %bb.1:
179-
; CHECKRV32ZDINX-NEXT: mv a0, a2
180-
; CHECKRV32ZDINX-NEXT: mv a1, a3
175+
; CHECKRV32ZDINX-NEXT: fmv.d a0, a2
181176
; CHECKRV32ZDINX-NEXT: .LBB5_2:
182177
; CHECKRV32ZDINX-NEXT: ret
183178
;
@@ -213,8 +208,7 @@ define double @select_fcmp_one(double %a, double %b) nounwind {
213208
; CHECKRV32ZDINX-NEXT: or a4, a5, a4
214209
; CHECKRV32ZDINX-NEXT: bnez a4, .LBB6_2
215210
; CHECKRV32ZDINX-NEXT: # %bb.1:
216-
; CHECKRV32ZDINX-NEXT: mv a0, a2
217-
; CHECKRV32ZDINX-NEXT: mv a1, a3
211+
; CHECKRV32ZDINX-NEXT: fmv.d a0, a2
218212
; CHECKRV32ZDINX-NEXT: .LBB6_2:
219213
; CHECKRV32ZDINX-NEXT: ret
220214
;
@@ -252,8 +246,7 @@ define double @select_fcmp_ord(double %a, double %b) nounwind {
252246
; CHECKRV32ZDINX-NEXT: and a4, a5, a4
253247
; CHECKRV32ZDINX-NEXT: bnez a4, .LBB7_2
254248
; CHECKRV32ZDINX-NEXT: # %bb.1:
255-
; CHECKRV32ZDINX-NEXT: mv a0, a2
256-
; CHECKRV32ZDINX-NEXT: mv a1, a3
249+
; CHECKRV32ZDINX-NEXT: fmv.d a0, a2
257250
; CHECKRV32ZDINX-NEXT: .LBB7_2:
258251
; CHECKRV32ZDINX-NEXT: ret
259252
;
@@ -291,8 +284,7 @@ define double @select_fcmp_ueq(double %a, double %b) nounwind {
291284
; CHECKRV32ZDINX-NEXT: or a4, a5, a4
292285
; CHECKRV32ZDINX-NEXT: beqz a4, .LBB8_2
293286
; CHECKRV32ZDINX-NEXT: # %bb.1:
294-
; CHECKRV32ZDINX-NEXT: mv a0, a2
295-
; CHECKRV32ZDINX-NEXT: mv a1, a3
287+
; CHECKRV32ZDINX-NEXT: fmv.d a0, a2
296288
; CHECKRV32ZDINX-NEXT: .LBB8_2:
297289
; CHECKRV32ZDINX-NEXT: ret
298290
;
@@ -326,8 +318,7 @@ define double @select_fcmp_ugt(double %a, double %b) nounwind {
326318
; CHECKRV32ZDINX-NEXT: fle.d a4, a0, a2
327319
; CHECKRV32ZDINX-NEXT: beqz a4, .LBB9_2
328320
; CHECKRV32ZDINX-NEXT: # %bb.1:
329-
; CHECKRV32ZDINX-NEXT: mv a0, a2
330-
; CHECKRV32ZDINX-NEXT: mv a1, a3
321+
; CHECKRV32ZDINX-NEXT: fmv.d a0, a2
331322
; CHECKRV32ZDINX-NEXT: .LBB9_2:
332323
; CHECKRV32ZDINX-NEXT: ret
333324
;
@@ -359,8 +350,7 @@ define double @select_fcmp_uge(double %a, double %b) nounwind {
359350
; CHECKRV32ZDINX-NEXT: flt.d a4, a0, a2
360351
; CHECKRV32ZDINX-NEXT: beqz a4, .LBB10_2
361352
; CHECKRV32ZDINX-NEXT: # %bb.1:
362-
; CHECKRV32ZDINX-NEXT: mv a0, a2
363-
; CHECKRV32ZDINX-NEXT: mv a1, a3
353+
; CHECKRV32ZDINX-NEXT: fmv.d a0, a2
364354
; CHECKRV32ZDINX-NEXT: .LBB10_2:
365355
; CHECKRV32ZDINX-NEXT: ret
366356
;
@@ -392,8 +382,7 @@ define double @select_fcmp_ult(double %a, double %b) nounwind {
392382
; CHECKRV32ZDINX-NEXT: fle.d a4, a2, a0
393383
; CHECKRV32ZDINX-NEXT: beqz a4, .LBB11_2
394384
; CHECKRV32ZDINX-NEXT: # %bb.1:
395-
; CHECKRV32ZDINX-NEXT: mv a0, a2
396-
; CHECKRV32ZDINX-NEXT: mv a1, a3
385+
; CHECKRV32ZDINX-NEXT: fmv.d a0, a2
397386
; CHECKRV32ZDINX-NEXT: .LBB11_2:
398387
; CHECKRV32ZDINX-NEXT: ret
399388
;
@@ -425,8 +414,7 @@ define double @select_fcmp_ule(double %a, double %b) nounwind {
425414
; CHECKRV32ZDINX-NEXT: flt.d a4, a2, a0
426415
; CHECKRV32ZDINX-NEXT: beqz a4, .LBB12_2
427416
; CHECKRV32ZDINX-NEXT: # %bb.1:
428-
; CHECKRV32ZDINX-NEXT: mv a0, a2
429-
; CHECKRV32ZDINX-NEXT: mv a1, a3
417+
; CHECKRV32ZDINX-NEXT: fmv.d a0, a2
430418
; CHECKRV32ZDINX-NEXT: .LBB12_2:
431419
; CHECKRV32ZDINX-NEXT: ret
432420
;
@@ -458,8 +446,7 @@ define double @select_fcmp_une(double %a, double %b) nounwind {
458446
; CHECKRV32ZDINX-NEXT: feq.d a4, a0, a2
459447
; CHECKRV32ZDINX-NEXT: beqz a4, .LBB13_2
460448
; CHECKRV32ZDINX-NEXT: # %bb.1:
461-
; CHECKRV32ZDINX-NEXT: mv a0, a2
462-
; CHECKRV32ZDINX-NEXT: mv a1, a3
449+
; CHECKRV32ZDINX-NEXT: fmv.d a0, a2
463450
; CHECKRV32ZDINX-NEXT: .LBB13_2:
464451
; CHECKRV32ZDINX-NEXT: ret
465452
;
@@ -495,8 +482,7 @@ define double @select_fcmp_uno(double %a, double %b) nounwind {
495482
; CHECKRV32ZDINX-NEXT: and a4, a5, a4
496483
; CHECKRV32ZDINX-NEXT: beqz a4, .LBB14_2
497484
; CHECKRV32ZDINX-NEXT: # %bb.1:
498-
; CHECKRV32ZDINX-NEXT: mv a0, a2
499-
; CHECKRV32ZDINX-NEXT: mv a1, a3
485+
; CHECKRV32ZDINX-NEXT: fmv.d a0, a2
500486
; CHECKRV32ZDINX-NEXT: .LBB14_2:
501487
; CHECKRV32ZDINX-NEXT: ret
502488
;
@@ -683,12 +669,10 @@ define double @CascadedSelect(double noundef %a) {
683669
; CHECKRV32ZDINX-NEXT: bnez a4, .LBB20_3
684670
; CHECKRV32ZDINX-NEXT: # %bb.1: # %entry
685671
; CHECKRV32ZDINX-NEXT: flt.d a4, a0, zero
686-
; CHECKRV32ZDINX-NEXT: li a2, 0
687-
; CHECKRV32ZDINX-NEXT: li a3, 0
672+
; CHECKRV32ZDINX-NEXT: fmv.d a2, zero
688673
; CHECKRV32ZDINX-NEXT: bnez a4, .LBB20_3
689674
; CHECKRV32ZDINX-NEXT: # %bb.2: # %entry
690-
; CHECKRV32ZDINX-NEXT: mv a2, a0
691-
; CHECKRV32ZDINX-NEXT: mv a3, a1
675+
; CHECKRV32ZDINX-NEXT: fmv.d a2, a0
692676
; CHECKRV32ZDINX-NEXT: .LBB20_3: # %entry
693677
; CHECKRV32ZDINX-NEXT: mv a0, a2
694678
; CHECKRV32ZDINX-NEXT: mv a1, a3

‎llvm/test/CodeGen/RISCV/double-select-icmp.ll‎

Lines changed: 10 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -22,8 +22,7 @@ define double @select_icmp_eq(i32 signext %a, i32 signext %b, double %c, double
2222
; RV32ZDINX: # %bb.0:
2323
; RV32ZDINX-NEXT: beq a0, a1, .LBB0_2
2424
; RV32ZDINX-NEXT: # %bb.1:
25-
; RV32ZDINX-NEXT: mv a2, a4
26-
; RV32ZDINX-NEXT: mv a3, a5
25+
; RV32ZDINX-NEXT: fmv.d a2, a4
2726
; RV32ZDINX-NEXT: .LBB0_2:
2827
; RV32ZDINX-NEXT: mv a0, a2
2928
; RV32ZDINX-NEXT: mv a1, a3
@@ -55,8 +54,7 @@ define double @select_icmp_ne(i32 signext %a, i32 signext %b, double %c, double
5554
; RV32ZDINX: # %bb.0:
5655
; RV32ZDINX-NEXT: bne a0, a1, .LBB1_2
5756
; RV32ZDINX-NEXT: # %bb.1:
58-
; RV32ZDINX-NEXT: mv a2, a4
59-
; RV32ZDINX-NEXT: mv a3, a5
57+
; RV32ZDINX-NEXT: fmv.d a2, a4
6058
; RV32ZDINX-NEXT: .LBB1_2:
6159
; RV32ZDINX-NEXT: mv a0, a2
6260
; RV32ZDINX-NEXT: mv a1, a3
@@ -88,8 +86,7 @@ define double @select_icmp_ugt(i32 signext %a, i32 signext %b, double %c, double
8886
; RV32ZDINX: # %bb.0:
8987
; RV32ZDINX-NEXT: bltu a1, a0, .LBB2_2
9088
; RV32ZDINX-NEXT: # %bb.1:
91-
; RV32ZDINX-NEXT: mv a2, a4
92-
; RV32ZDINX-NEXT: mv a3, a5
89+
; RV32ZDINX-NEXT: fmv.d a2, a4
9390
; RV32ZDINX-NEXT: .LBB2_2:
9491
; RV32ZDINX-NEXT: mv a0, a2
9592
; RV32ZDINX-NEXT: mv a1, a3
@@ -121,8 +118,7 @@ define double @select_icmp_uge(i32 signext %a, i32 signext %b, double %c, double
121118
; RV32ZDINX: # %bb.0:
122119
; RV32ZDINX-NEXT: bgeu a0, a1, .LBB3_2
123120
; RV32ZDINX-NEXT: # %bb.1:
124-
; RV32ZDINX-NEXT: mv a2, a4
125-
; RV32ZDINX-NEXT: mv a3, a5
121+
; RV32ZDINX-NEXT: fmv.d a2, a4
126122
; RV32ZDINX-NEXT: .LBB3_2:
127123
; RV32ZDINX-NEXT: mv a0, a2
128124
; RV32ZDINX-NEXT: mv a1, a3
@@ -154,8 +150,7 @@ define double @select_icmp_ult(i32 signext %a, i32 signext %b, double %c, double
154150
; RV32ZDINX: # %bb.0:
155151
; RV32ZDINX-NEXT: bltu a0, a1, .LBB4_2
156152
; RV32ZDINX-NEXT: # %bb.1:
157-
; RV32ZDINX-NEXT: mv a2, a4
158-
; RV32ZDINX-NEXT: mv a3, a5
153+
; RV32ZDINX-NEXT: fmv.d a2, a4
159154
; RV32ZDINX-NEXT: .LBB4_2:
160155
; RV32ZDINX-NEXT: mv a0, a2
161156
; RV32ZDINX-NEXT: mv a1, a3
@@ -187,8 +182,7 @@ define double @select_icmp_ule(i32 signext %a, i32 signext %b, double %c, double
187182
; RV32ZDINX: # %bb.0:
188183
; RV32ZDINX-NEXT: bgeu a1, a0, .LBB5_2
189184
; RV32ZDINX-NEXT: # %bb.1:
190-
; RV32ZDINX-NEXT: mv a2, a4
191-
; RV32ZDINX-NEXT: mv a3, a5
185+
; RV32ZDINX-NEXT: fmv.d a2, a4
192186
; RV32ZDINX-NEXT: .LBB5_2:
193187
; RV32ZDINX-NEXT: mv a0, a2
194188
; RV32ZDINX-NEXT: mv a1, a3
@@ -220,8 +214,7 @@ define double @select_icmp_sgt(i32 signext %a, i32 signext %b, double %c, double
220214
; RV32ZDINX: # %bb.0:
221215
; RV32ZDINX-NEXT: blt a1, a0, .LBB6_2
222216
; RV32ZDINX-NEXT: # %bb.1:
223-
; RV32ZDINX-NEXT: mv a2, a4
224-
; RV32ZDINX-NEXT: mv a3, a5
217+
; RV32ZDINX-NEXT: fmv.d a2, a4
225218
; RV32ZDINX-NEXT: .LBB6_2:
226219
; RV32ZDINX-NEXT: mv a0, a2
227220
; RV32ZDINX-NEXT: mv a1, a3
@@ -253,8 +246,7 @@ define double @select_icmp_sge(i32 signext %a, i32 signext %b, double %c, double
253246
; RV32ZDINX: # %bb.0:
254247
; RV32ZDINX-NEXT: bge a0, a1, .LBB7_2
255248
; RV32ZDINX-NEXT: # %bb.1:
256-
; RV32ZDINX-NEXT: mv a2, a4
257-
; RV32ZDINX-NEXT: mv a3, a5
249+
; RV32ZDINX-NEXT: fmv.d a2, a4
258250
; RV32ZDINX-NEXT: .LBB7_2:
259251
; RV32ZDINX-NEXT: mv a0, a2
260252
; RV32ZDINX-NEXT: mv a1, a3
@@ -286,8 +278,7 @@ define double @select_icmp_slt(i32 signext %a, i32 signext %b, double %c, double
286278
; RV32ZDINX: # %bb.0:
287279
; RV32ZDINX-NEXT: blt a0, a1, .LBB8_2
288280
; RV32ZDINX-NEXT: # %bb.1:
289-
; RV32ZDINX-NEXT: mv a2, a4
290-
; RV32ZDINX-NEXT: mv a3, a5
281+
; RV32ZDINX-NEXT: fmv.d a2, a4
291282
; RV32ZDINX-NEXT: .LBB8_2:
292283
; RV32ZDINX-NEXT: mv a0, a2
293284
; RV32ZDINX-NEXT: mv a1, a3
@@ -319,8 +310,7 @@ define double @select_icmp_sle(i32 signext %a, i32 signext %b, double %c, double
319310
; RV32ZDINX: # %bb.0:
320311
; RV32ZDINX-NEXT: bge a1, a0, .LBB9_2
321312
; RV32ZDINX-NEXT: # %bb.1:
322-
; RV32ZDINX-NEXT: mv a2, a4
323-
; RV32ZDINX-NEXT: mv a3, a5
313+
; RV32ZDINX-NEXT: fmv.d a2, a4
324314
; RV32ZDINX-NEXT: .LBB9_2:
325315
; RV32ZDINX-NEXT: mv a0, a2
326316
; RV32ZDINX-NEXT: mv a1, a3

‎llvm/test/CodeGen/RISCV/fold-addi-loadstore-zilsd.ll‎

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -44,8 +44,7 @@ define double @fold_addi_from_different_bb(i32 %k, i32 %n, ptr %a) nounwind {
4444
; CHECK-NEXT: # %bb.1: # %for.body.lr.ph
4545
; CHECK-NEXT: mv s2, a2
4646
; CHECK-NEXT: mv s3, a1
47-
; CHECK-NEXT: li s0, 0
48-
; CHECK-NEXT: li s1, 0
47+
; CHECK-NEXT: fmv.d s0, zero
4948
; CHECK-NEXT: slli a0, a0, 4
5049
; CHECK-NEXT: add s4, a2, a0
5150
; CHECK-NEXT: .LBB2_2: # %for.body
@@ -58,8 +57,7 @@ define double @fold_addi_from_different_bb(i32 %k, i32 %n, ptr %a) nounwind {
5857
; CHECK-NEXT: bnez s3, .LBB2_2
5958
; CHECK-NEXT: j .LBB2_4
6059
; CHECK-NEXT: .LBB2_3:
61-
; CHECK-NEXT: li s0, 0
62-
; CHECK-NEXT: li s1, 0
60+
; CHECK-NEXT: fmv.d s0, zero
6361
; CHECK-NEXT: .LBB2_4: # %for.cond.cleanup
6462
; CHECK-NEXT: mv a0, s0
6563
; CHECK-NEXT: mv a1, s1

‎llvm/test/CodeGen/RISCV/make-compressible-zilsd.mir‎

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -121,8 +121,7 @@ body: |
121121
; RV32-LABEL: name: store_common_value_double
122122
; RV32: liveins: $x10, $x11, $x12, $x16, $x17
123123
; RV32-NEXT: {{ $}}
124-
; RV32-NEXT: $x14 = ADDI $x16, 0
125-
; RV32-NEXT: $x15 = ADDI $x17, 0
124+
; RV32-NEXT: $x14_x15 = FSGNJ_D_IN32X $x16_x17, $x16_x17
126125
; RV32-NEXT: SD_RV32 $x14_x15, killed renamable $x10, 0 :: (store (s64) into %ir.a)
127126
; RV32-NEXT: SD_RV32 $x14_x15, killed renamable $x11, 0 :: (store (s64) into %ir.b)
128127
; RV32-NEXT: SD_RV32 killed $x14_x15, killed renamable $x12, 0 :: (store (s64) into %ir.c)
@@ -143,8 +142,7 @@ body: |
143142
; RV32-LABEL: name: store_common_value_double_zero
144143
; RV32: liveins: $x10, $x11, $x12
145144
; RV32-NEXT: {{ $}}
146-
; RV32-NEXT: $x14 = ADDI $x0, 0
147-
; RV32-NEXT: $x15 = ADDI $x0, 0
145+
; RV32-NEXT: $x14_x15 = FSGNJ_D_IN32X $x0_pair, $x0_pair
148146
; RV32-NEXT: SD_RV32 $x14_x15, killed renamable $x10, 0 :: (store (s64) into %ir.a)
149147
; RV32-NEXT: SD_RV32 $x14_x15, killed renamable $x11, 0 :: (store (s64) into %ir.b)
150148
; RV32-NEXT: SD_RV32 $x14_x15, killed renamable $x12, 0 :: (store (s64) into %ir.c)

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