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[AMDGPU] Remove implicit conversions of MCRegister to unsigned. NFC (llvm#167284)
Use MCRegister instead of MCPhysReg or use MCRegister::id().
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6 files changed

+41
-40
lines changed

6 files changed

+41
-40
lines changed

‎llvm/lib/Target/AMDGPU/AMDGPUArgumentUsageInfo.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -52,7 +52,7 @@ struct ArgDescriptor {
5252
}
5353

5454
static ArgDescriptor createArg(const ArgDescriptor &Arg, unsigned Mask) {
55-
return ArgDescriptor(Arg.Reg, Mask, Arg.IsStack, Arg.IsSet);
55+
return ArgDescriptor(Arg.Reg.id(), Mask, Arg.IsStack, Arg.IsSet);
5656
}
5757

5858
bool isSet() const {

‎llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp‎

Lines changed: 5 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1199,8 +1199,8 @@ void AMDGPUDisassembler::convertVOP3DPPInst(MCInst &MI) const {
11991199

12001200
// Given a wide tuple \p Reg check if it will overflow 256 registers.
12011201
// \returns \p Reg on success or NoRegister otherwise.
1202-
static unsigned CheckVGPROverflow(unsigned Reg, const MCRegisterClass &RC,
1203-
const MCRegisterInfo &MRI) {
1202+
static MCRegister CheckVGPROverflow(MCRegister Reg, const MCRegisterClass &RC,
1203+
const MCRegisterInfo &MRI) {
12041204
unsigned NumRegs = RC.getSizeInBits() / 32;
12051205
MCRegister Sub0 = MRI.getSubReg(Reg, AMDGPU::sub0);
12061206
if (!Sub0)
@@ -1214,7 +1214,7 @@ static unsigned CheckVGPROverflow(unsigned Reg, const MCRegisterClass &RC,
12141214

12151215
assert(BaseReg && "Only vector registers expected");
12161216

1217-
return (Sub0 - BaseReg + NumRegs <= 256) ? Reg : AMDGPU::NoRegister;
1217+
return (Sub0 - BaseReg + NumRegs <= 256) ? Reg : MCRegister();
12181218
}
12191219

12201220
// Note that before gfx10, the MIMG encoding provided no information about
@@ -1456,9 +1456,8 @@ MCOperand AMDGPUDisassembler::errOperand(unsigned V,
14561456
return MCOperand();
14571457
}
14581458

1459-
inline
1460-
MCOperand AMDGPUDisassembler::createRegOperand(unsigned int RegId) const {
1461-
return MCOperand::createReg(AMDGPU::getMCReg(RegId, STI));
1459+
inline MCOperand AMDGPUDisassembler::createRegOperand(MCRegister Reg) const {
1460+
return MCOperand::createReg(AMDGPU::getMCReg(Reg, STI));
14621461
}
14631462

14641463
inline

‎llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -69,7 +69,7 @@ class AMDGPUDisassembler : public MCDisassembler {
6969

7070
const char* getRegClassName(unsigned RegClassID) const;
7171

72-
MCOperand createRegOperand(unsigned int RegId) const;
72+
MCOperand createRegOperand(MCRegister Reg) const;
7373
MCOperand createRegOperand(unsigned RegClassID, unsigned Val) const;
7474
MCOperand createSRegOperand(unsigned SRegClassID, unsigned Val) const;
7575
MCOperand createVGPR16Operand(unsigned RegIdx, bool IsHi) const;

‎llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp‎

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -336,7 +336,7 @@ void AMDGPUInstPrinter::printSymbolicFormat(const MCInst *MI,
336336

337337
// \returns a low 256 vgpr representing a high vgpr \p Reg [v256..v1023] or
338338
// \p Reg itself otherwise.
339-
static MCPhysReg getRegForPrinting(MCPhysReg Reg, const MCRegisterInfo &MRI) {
339+
static MCRegister getRegForPrinting(MCRegister Reg, const MCRegisterInfo &MRI) {
340340
unsigned Enc = MRI.getEncodingValue(Reg);
341341
unsigned Idx = Enc & AMDGPU::HWEncoding::REG_IDX_MASK;
342342
if (Idx < 0x100)
@@ -355,10 +355,10 @@ static MCPhysReg getRegForPrinting(MCPhysReg Reg, const MCRegisterInfo &MRI) {
355355
}
356356

357357
// Restore MSBs of a VGPR above 255 from the MCInstrAnalysis.
358-
static MCPhysReg getRegFromMIA(MCPhysReg Reg, unsigned OpNo,
359-
const MCInstrDesc &Desc,
360-
const MCRegisterInfo &MRI,
361-
const AMDGPUMCInstrAnalysis &MIA) {
358+
static MCRegister getRegFromMIA(MCRegister Reg, unsigned OpNo,
359+
const MCInstrDesc &Desc,
360+
const MCRegisterInfo &MRI,
361+
const AMDGPUMCInstrAnalysis &MIA) {
362362
unsigned VgprMSBs = MIA.getVgprMSBs();
363363
if (!VgprMSBs)
364364
return Reg;
@@ -403,10 +403,10 @@ void AMDGPUInstPrinter::printRegOperand(MCRegister Reg, raw_ostream &O,
403403
}
404404
#endif
405405

406-
unsigned PrintReg = getRegForPrinting(Reg, MRI);
406+
MCRegister PrintReg = getRegForPrinting(Reg, MRI);
407407
O << getRegisterName(PrintReg);
408408

409-
if (PrintReg != Reg.id())
409+
if (PrintReg != Reg)
410410
O << " /*" << getRegisterName(Reg) << "*/";
411411
}
412412

‎llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp‎

Lines changed: 15 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -897,7 +897,7 @@ unsigned ComponentInfo::getIndexInParsedOperands(unsigned CompOprIdx) const {
897897
}
898898

899899
std::optional<unsigned> InstInfo::getInvalidCompOperandIndex(
900-
std::function<unsigned(unsigned, unsigned)> GetRegIdx,
900+
std::function<MCRegister(unsigned, unsigned)> GetRegIdx,
901901
const MCRegisterInfo &MRI, bool SkipSrc, bool AllowSameVGPR,
902902
bool VOPD3) const {
903903

@@ -914,12 +914,13 @@ std::optional<unsigned> InstInfo::getInvalidCompOperandIndex(
914914
BaseX = X;
915915
if (!BaseY)
916916
BaseY = Y;
917-
if ((BaseX & BanksMask) == (BaseY & BanksMask))
917+
if ((BaseX.id() & BanksMask) == (BaseY.id() & BanksMask))
918918
return true;
919919
if (BaseX != X /* This is 64-bit register */ &&
920-
((BaseX + 1) & BanksMask) == (BaseY & BanksMask))
920+
((BaseX.id() + 1) & BanksMask) == (BaseY.id() & BanksMask))
921921
return true;
922-
if (BaseY != Y && (BaseX & BanksMask) == ((BaseY + 1) & BanksMask))
922+
if (BaseY != Y &&
923+
(BaseX.id() & BanksMask) == ((BaseY.id() + 1) & BanksMask))
923924
return true;
924925

925926
// If both are 64-bit bank conflict will be detected yet while checking
@@ -968,7 +969,7 @@ std::optional<unsigned> InstInfo::getInvalidCompOperandIndex(
968969
// if the operand is not a register or not a VGPR.
969970
InstInfo::RegIndices
970971
InstInfo::getRegIndices(unsigned CompIdx,
971-
std::function<unsigned(unsigned, unsigned)> GetRegIdx,
972+
std::function<MCRegister(unsigned, unsigned)> GetRegIdx,
972973
bool VOPD3) const {
973974
assert(CompIdx < COMPONENTS_NUM);
974975

@@ -983,7 +984,7 @@ InstInfo::getRegIndices(unsigned CompIdx,
983984
Comp.hasRegSrcOperand(CompSrcIdx)
984985
? GetRegIdx(CompIdx,
985986
Comp.getIndexOfSrcInMCOperands(CompSrcIdx, VOPD3))
986-
: 0;
987+
: MCRegister();
987988
}
988989
return RegIndices;
989990
}
@@ -2697,8 +2698,8 @@ MCRegister getMCReg(MCRegister Reg, const MCSubtargetInfo &STI) {
26972698

26982699
MCRegister mc2PseudoReg(MCRegister Reg) { MAP_REG2REG }
26992700

2700-
bool isInlineValue(unsigned Reg) {
2701-
switch (Reg) {
2701+
bool isInlineValue(MCRegister Reg) {
2702+
switch (Reg.id()) {
27022703
case AMDGPU::SRC_SHARED_BASE_LO:
27032704
case AMDGPU::SRC_SHARED_BASE:
27042705
case AMDGPU::SRC_SHARED_LIMIT_LO:
@@ -3361,7 +3362,7 @@ const GcnBufferFormatInfo *getGcnBufferFormatInfo(uint8_t Format,
33613362
: getGfx9BufferFormatInfo(Format);
33623363
}
33633364

3364-
const MCRegisterClass *getVGPRPhysRegClass(MCPhysReg Reg,
3365+
const MCRegisterClass *getVGPRPhysRegClass(MCRegister Reg,
33653366
const MCRegisterInfo &MRI) {
33663367
const unsigned VGPRClasses[] = {
33673368
AMDGPU::VGPR_16RegClassID, AMDGPU::VGPR_32RegClassID,
@@ -3382,22 +3383,22 @@ const MCRegisterClass *getVGPRPhysRegClass(MCPhysReg Reg,
33823383
return nullptr;
33833384
}
33843385

3385-
unsigned getVGPREncodingMSBs(MCPhysReg Reg, const MCRegisterInfo &MRI) {
3386+
unsigned getVGPREncodingMSBs(MCRegister Reg, const MCRegisterInfo &MRI) {
33863387
unsigned Enc = MRI.getEncodingValue(Reg);
33873388
unsigned Idx = Enc & AMDGPU::HWEncoding::REG_IDX_MASK;
33883389
return Idx >> 8;
33893390
}
33903391

3391-
MCPhysReg getVGPRWithMSBs(MCPhysReg Reg, unsigned MSBs,
3392-
const MCRegisterInfo &MRI) {
3392+
MCRegister getVGPRWithMSBs(MCRegister Reg, unsigned MSBs,
3393+
const MCRegisterInfo &MRI) {
33933394
unsigned Enc = MRI.getEncodingValue(Reg);
33943395
unsigned Idx = Enc & AMDGPU::HWEncoding::REG_IDX_MASK;
33953396
if (Idx >= 0x100)
3396-
return AMDGPU::NoRegister;
3397+
return MCRegister();
33973398

33983399
const MCRegisterClass *RC = getVGPRPhysRegClass(Reg, MRI);
33993400
if (!RC)
3400-
return AMDGPU::NoRegister;
3401+
return MCRegister();
34013402

34023403
Idx |= MSBs << 8;
34033404
if (RC->getID() == AMDGPU::VGPR_16RegClassID) {

‎llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h‎

Lines changed: 12 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -909,7 +909,7 @@ class InstInfo {
909909
const ComponentInfo CompInfo[COMPONENTS_NUM];
910910

911911
public:
912-
using RegIndices = std::array<unsigned, Component::MAX_OPR_NUM>;
912+
using RegIndices = std::array<MCRegister, Component::MAX_OPR_NUM>;
913913

914914
InstInfo(const MCInstrDesc &OpX, const MCInstrDesc &OpY)
915915
: CompInfo{OpX, OpY} {}
@@ -932,9 +932,10 @@ class InstInfo {
932932
// even though it violates requirement to be from different banks.
933933
// If \p VOPD3 is set to true both dst registers allowed to be either odd
934934
// or even and instruction may have real src2 as opposed to tied accumulator.
935-
bool hasInvalidOperand(std::function<unsigned(unsigned, unsigned)> GetRegIdx,
936-
const MCRegisterInfo &MRI, bool SkipSrc = false,
937-
bool AllowSameVGPR = false, bool VOPD3 = false) const {
935+
bool
936+
hasInvalidOperand(std::function<MCRegister(unsigned, unsigned)> GetRegIdx,
937+
const MCRegisterInfo &MRI, bool SkipSrc = false,
938+
bool AllowSameVGPR = false, bool VOPD3 = false) const {
938939
return getInvalidCompOperandIndex(GetRegIdx, MRI, SkipSrc, AllowSameVGPR,
939940
VOPD3)
940941
.has_value();
@@ -949,14 +950,14 @@ class InstInfo {
949950
// If \p VOPD3 is set to true both dst registers allowed to be either odd
950951
// or even and instruction may have real src2 as opposed to tied accumulator.
951952
std::optional<unsigned> getInvalidCompOperandIndex(
952-
std::function<unsigned(unsigned, unsigned)> GetRegIdx,
953+
std::function<MCRegister(unsigned, unsigned)> GetRegIdx,
953954
const MCRegisterInfo &MRI, bool SkipSrc = false,
954955
bool AllowSameVGPR = false, bool VOPD3 = false) const;
955956

956957
private:
957958
RegIndices
958959
getRegIndices(unsigned ComponentIdx,
959-
std::function<unsigned(unsigned, unsigned)> GetRegIdx,
960+
std::function<MCRegister(unsigned, unsigned)> GetRegIdx,
960961
bool VOPD3) const;
961962
};
962963

@@ -1599,7 +1600,7 @@ LLVM_READNONE
15991600
MCRegister mc2PseudoReg(MCRegister Reg);
16001601

16011602
LLVM_READNONE
1602-
bool isInlineValue(unsigned Reg);
1603+
bool isInlineValue(MCRegister Reg);
16031604

16041605
/// Is this an AMDGPU specific source operand? These include registers,
16051606
/// inline constants, literals and mandatory literals (KImm).
@@ -1798,16 +1799,16 @@ bool isIntrinsicAlwaysUniform(unsigned IntrID);
17981799

17991800
/// \returns a register class for the physical register \p Reg if it is a VGPR
18001801
/// or nullptr otherwise.
1801-
const MCRegisterClass *getVGPRPhysRegClass(MCPhysReg Reg,
1802+
const MCRegisterClass *getVGPRPhysRegClass(MCRegister Reg,
18021803
const MCRegisterInfo &MRI);
18031804

18041805
/// \returns the MODE bits which have to be set by the S_SET_VGPR_MSB for the
18051806
/// physical register \p Reg.
1806-
unsigned getVGPREncodingMSBs(MCPhysReg Reg, const MCRegisterInfo &MRI);
1807+
unsigned getVGPREncodingMSBs(MCRegister Reg, const MCRegisterInfo &MRI);
18071808

18081809
/// If \p Reg is a low VGPR return a corresponding high VGPR with \p MSBs set.
1809-
MCPhysReg getVGPRWithMSBs(MCPhysReg Reg, unsigned MSBs,
1810-
const MCRegisterInfo &MRI);
1810+
MCRegister getVGPRWithMSBs(MCRegister Reg, unsigned MSBs,
1811+
const MCRegisterInfo &MRI);
18111812

18121813
// Returns a table for the opcode with a given \p Desc to map the VGPR MSB
18131814
// set by the S_SET_VGPR_MSB to one of 4 sources. In case of VOPD returns 2

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