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[AArch64] Combine ADDS and SUBS nodes with the non-flag setting versions (llvm#157563)
We do that with the other flag setting nodes. We should do this with all flag setting and non-flag setting nodes.
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6 files changed

+32
-34
lines changed

6 files changed

+32
-34
lines changed

‎llvm/lib/Target/AArch64/AArch64ISelLowering.cpp‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -27572,6 +27572,10 @@ SDValue AArch64TargetLowering::PerformDAGCombine(SDNode *N,
2757227572
if (auto R = foldOverflowCheck(N, DAG, /* IsAdd */ false))
2757327573
return R;
2757427574
return performFlagSettingCombine(N, DCI, AArch64ISD::SBC);
27575+
case AArch64ISD::ADDS:
27576+
return performFlagSettingCombine(N, DCI, ISD::ADD);
27577+
case AArch64ISD::SUBS:
27578+
return performFlagSettingCombine(N, DCI, ISD::SUB);
2757527579
case AArch64ISD::BICi: {
2757627580
APInt DemandedBits =
2757727581
APInt::getAllOnes(N->getValueType(0).getScalarSizeInBits());

‎llvm/test/CodeGen/AArch64/abds-neg.ll‎

Lines changed: 12 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -73,8 +73,8 @@ define i16 @abd_ext_i16_i32(i16 %a, i32 %b) nounwind {
7373
; CHECK-LABEL: abd_ext_i16_i32:
7474
; CHECK: // %bb.0:
7575
; CHECK-NEXT: sxth w8, w0
76-
; CHECK-NEXT: subs w8, w1, w8
77-
; CHECK-NEXT: cneg w0, w8, ge
76+
; CHECK-NEXT: subs w8, w8, w1
77+
; CHECK-NEXT: cneg w0, w8, gt
7878
; CHECK-NEXT: ret
7979
%aext = sext i16 %a to i64
8080
%bext = sext i32 %b to i64
@@ -104,8 +104,8 @@ define i16 @abd_ext_i16_undef(i16 %a, i16 %b) nounwind {
104104
define i32 @abd_ext_i32(i32 %a, i32 %b) nounwind {
105105
; CHECK-LABEL: abd_ext_i32:
106106
; CHECK: // %bb.0:
107-
; CHECK-NEXT: subs w8, w1, w0
108-
; CHECK-NEXT: cneg w0, w8, ge
107+
; CHECK-NEXT: subs w8, w0, w1
108+
; CHECK-NEXT: cneg w0, w8, gt
109109
; CHECK-NEXT: ret
110110
%aext = sext i32 %a to i64
111111
%bext = sext i32 %b to i64
@@ -119,9 +119,8 @@ define i32 @abd_ext_i32(i32 %a, i32 %b) nounwind {
119119
define i32 @abd_ext_i32_i16(i32 %a, i16 %b) nounwind {
120120
; CHECK-LABEL: abd_ext_i32_i16:
121121
; CHECK: // %bb.0:
122-
; CHECK-NEXT: sxth w8, w1
123-
; CHECK-NEXT: subs w8, w8, w0
124-
; CHECK-NEXT: cneg w0, w8, ge
122+
; CHECK-NEXT: subs w8, w0, w1, sxth
123+
; CHECK-NEXT: cneg w0, w8, gt
125124
; CHECK-NEXT: ret
126125
%aext = sext i32 %a to i64
127126
%bext = sext i16 %b to i64
@@ -135,8 +134,8 @@ define i32 @abd_ext_i32_i16(i32 %a, i16 %b) nounwind {
135134
define i32 @abd_ext_i32_undef(i32 %a, i32 %b) nounwind {
136135
; CHECK-LABEL: abd_ext_i32_undef:
137136
; CHECK: // %bb.0:
138-
; CHECK-NEXT: subs w8, w1, w0
139-
; CHECK-NEXT: cneg w0, w8, ge
137+
; CHECK-NEXT: subs w8, w0, w1
138+
; CHECK-NEXT: cneg w0, w8, gt
140139
; CHECK-NEXT: ret
141140
%aext = sext i32 %a to i64
142141
%bext = sext i32 %b to i64
@@ -150,8 +149,8 @@ define i32 @abd_ext_i32_undef(i32 %a, i32 %b) nounwind {
150149
define i64 @abd_ext_i64(i64 %a, i64 %b) nounwind {
151150
; CHECK-LABEL: abd_ext_i64:
152151
; CHECK: // %bb.0:
153-
; CHECK-NEXT: subs x8, x1, x0
154-
; CHECK-NEXT: cneg x0, x8, ge
152+
; CHECK-NEXT: subs x8, x0, x1
153+
; CHECK-NEXT: cneg x0, x8, gt
155154
; CHECK-NEXT: ret
156155
%aext = sext i64 %a to i128
157156
%bext = sext i64 %b to i128
@@ -165,8 +164,8 @@ define i64 @abd_ext_i64(i64 %a, i64 %b) nounwind {
165164
define i64 @abd_ext_i64_undef(i64 %a, i64 %b) nounwind {
166165
; CHECK-LABEL: abd_ext_i64_undef:
167166
; CHECK: // %bb.0:
168-
; CHECK-NEXT: subs x8, x1, x0
169-
; CHECK-NEXT: cneg x0, x8, ge
167+
; CHECK-NEXT: subs x8, x0, x1
168+
; CHECK-NEXT: cneg x0, x8, gt
170169
; CHECK-NEXT: ret
171170
%aext = sext i64 %a to i128
172171
%bext = sext i64 %b to i128

‎llvm/test/CodeGen/AArch64/abds.ll‎

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -112,8 +112,7 @@ define i32 @abd_ext_i32(i32 %a, i32 %b) nounwind {
112112
define i32 @abd_ext_i32_i16(i32 %a, i16 %b) nounwind {
113113
; CHECK-LABEL: abd_ext_i32_i16:
114114
; CHECK: // %bb.0:
115-
; CHECK-NEXT: sxth w8, w1
116-
; CHECK-NEXT: subs w8, w0, w8
115+
; CHECK-NEXT: subs w8, w0, w1, sxth
117116
; CHECK-NEXT: cneg w0, w8, le
118117
; CHECK-NEXT: ret
119118
%aext = sext i32 %a to i64

‎llvm/test/CodeGen/AArch64/abdu-neg.ll‎

Lines changed: 12 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -73,8 +73,8 @@ define i16 @abd_ext_i16_i32(i16 %a, i32 %b) nounwind {
7373
; CHECK-LABEL: abd_ext_i16_i32:
7474
; CHECK: // %bb.0:
7575
; CHECK-NEXT: and w8, w0, #0xffff
76-
; CHECK-NEXT: subs w8, w1, w8
77-
; CHECK-NEXT: cneg w0, w8, hs
76+
; CHECK-NEXT: subs w8, w8, w1
77+
; CHECK-NEXT: cneg w0, w8, hi
7878
; CHECK-NEXT: ret
7979
%aext = zext i16 %a to i64
8080
%bext = zext i32 %b to i64
@@ -104,8 +104,8 @@ define i16 @abd_ext_i16_undef(i16 %a, i16 %b) nounwind {
104104
define i32 @abd_ext_i32(i32 %a, i32 %b) nounwind {
105105
; CHECK-LABEL: abd_ext_i32:
106106
; CHECK: // %bb.0:
107-
; CHECK-NEXT: subs w8, w1, w0
108-
; CHECK-NEXT: cneg w0, w8, hs
107+
; CHECK-NEXT: subs w8, w0, w1
108+
; CHECK-NEXT: cneg w0, w8, hi
109109
; CHECK-NEXT: ret
110110
%aext = zext i32 %a to i64
111111
%bext = zext i32 %b to i64
@@ -119,9 +119,8 @@ define i32 @abd_ext_i32(i32 %a, i32 %b) nounwind {
119119
define i32 @abd_ext_i32_i16(i32 %a, i16 %b) nounwind {
120120
; CHECK-LABEL: abd_ext_i32_i16:
121121
; CHECK: // %bb.0:
122-
; CHECK-NEXT: and w8, w1, #0xffff
123-
; CHECK-NEXT: subs w8, w8, w0
124-
; CHECK-NEXT: cneg w0, w8, hs
122+
; CHECK-NEXT: subs w8, w0, w1, uxth
123+
; CHECK-NEXT: cneg w0, w8, hi
125124
; CHECK-NEXT: ret
126125
%aext = zext i32 %a to i64
127126
%bext = zext i16 %b to i64
@@ -135,8 +134,8 @@ define i32 @abd_ext_i32_i16(i32 %a, i16 %b) nounwind {
135134
define i32 @abd_ext_i32_undef(i32 %a, i32 %b) nounwind {
136135
; CHECK-LABEL: abd_ext_i32_undef:
137136
; CHECK: // %bb.0:
138-
; CHECK-NEXT: subs w8, w1, w0
139-
; CHECK-NEXT: cneg w0, w8, hs
137+
; CHECK-NEXT: subs w8, w0, w1
138+
; CHECK-NEXT: cneg w0, w8, hi
140139
; CHECK-NEXT: ret
141140
%aext = zext i32 %a to i64
142141
%bext = zext i32 %b to i64
@@ -150,8 +149,8 @@ define i32 @abd_ext_i32_undef(i32 %a, i32 %b) nounwind {
150149
define i64 @abd_ext_i64(i64 %a, i64 %b) nounwind {
151150
; CHECK-LABEL: abd_ext_i64:
152151
; CHECK: // %bb.0:
153-
; CHECK-NEXT: subs x8, x1, x0
154-
; CHECK-NEXT: cneg x0, x8, hs
152+
; CHECK-NEXT: subs x8, x0, x1
153+
; CHECK-NEXT: cneg x0, x8, hi
155154
; CHECK-NEXT: ret
156155
%aext = zext i64 %a to i128
157156
%bext = zext i64 %b to i128
@@ -165,8 +164,8 @@ define i64 @abd_ext_i64(i64 %a, i64 %b) nounwind {
165164
define i64 @abd_ext_i64_undef(i64 %a, i64 %b) nounwind {
166165
; CHECK-LABEL: abd_ext_i64_undef:
167166
; CHECK: // %bb.0:
168-
; CHECK-NEXT: subs x8, x1, x0
169-
; CHECK-NEXT: cneg x0, x8, hs
167+
; CHECK-NEXT: subs x8, x0, x1
168+
; CHECK-NEXT: cneg x0, x8, hi
170169
; CHECK-NEXT: ret
171170
%aext = zext i64 %a to i128
172171
%bext = zext i64 %b to i128

‎llvm/test/CodeGen/AArch64/abdu.ll‎

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -112,8 +112,7 @@ define i32 @abd_ext_i32(i32 %a, i32 %b) nounwind {
112112
define i32 @abd_ext_i32_i16(i32 %a, i16 %b) nounwind {
113113
; CHECK-LABEL: abd_ext_i32_i16:
114114
; CHECK: // %bb.0:
115-
; CHECK-NEXT: and w8, w1, #0xffff
116-
; CHECK-NEXT: subs w8, w0, w8
115+
; CHECK-NEXT: subs w8, w0, w1, uxth
117116
; CHECK-NEXT: cneg w0, w8, ls
118117
; CHECK-NEXT: ret
119118
%aext = zext i32 %a to i64

‎llvm/test/CodeGen/AArch64/adds_cmn.ll‎

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -4,10 +4,8 @@
44
define { i32, i32 } @adds_cmn(i32 noundef %x, i32 noundef %y) {
55
; CHECK-LABEL: adds_cmn:
66
; CHECK: // %bb.0: // %entry
7-
; CHECK-NEXT: cmn w0, w1
8-
; CHECK-NEXT: add w1, w0, w1
9-
; CHECK-NEXT: cset w8, lo
10-
; CHECK-NEXT: mov w0, w8
7+
; CHECK-NEXT: adds w1, w0, w1
8+
; CHECK-NEXT: cset w0, lo
119
; CHECK-NEXT: ret
1210
entry:
1311
%0 = tail call { i32, i1 } @llvm.uadd.with.overflow.i32(i32 %x, i32 %y)

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