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LowerTypeTests: Avoid zext of ptrtoint ConstantExpr.
In the LowerTypeTests pass we used to create IR like this: %3 = zext i8 ptrtoint (ptr @__typeid_allones7_align to i8) to i64 %4 = lshr i64 %2, %3 %5 = zext i8 sub (i8 64, i8 ptrtoint (ptr @__typeid_allones7_align to i8)) to i64 %6 = shl i64 %2, %5 %7 = or i64 %4, %6 This is because when this code was originally written there were no funnel shifts and as I recall it was necessary to create an i8 and zext to pointer width (instead of just having a ptrtoint of pointer width) in order for the shl/shr/or to be pattern matched to ror. At the time this caused no problems because there existed a zext ConstantExpr. But after zext ConstantExpr was removed in llvm#71040, the newly present zext instruction can prevent pattern matching the rotate, for example if the zext gets hoisted to a loop preheader or common ancestor of the check. LowerTypeTests was made to use fshr in llvm#141735 so now we can ptrtoint to pointer width and stop creating the zext. Reviewers: fmayer, nikic Reviewed By: nikic Pull Request: llvm#142886
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‎llvm/lib/Transforms/IPO/LowerTypeTests.cpp‎

Lines changed: 4 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -782,9 +782,8 @@ Value *LowerTypeTestsModule::lowerTypeTestCall(Metadata *TypeId, CallInst *CI,
782782
// result, causing the comparison to fail if they are nonzero. The rotate
783783
// also conveniently gives us a bit offset to use during the load from
784784
// the bitset.
785-
Value *BitOffset = B.CreateIntrinsic(
786-
IntPtrTy, Intrinsic::fshr,
787-
{PtrOffset, PtrOffset, B.CreateZExt(TIL.AlignLog2, IntPtrTy)});
785+
Value *BitOffset = B.CreateIntrinsic(IntPtrTy, Intrinsic::fshr,
786+
{PtrOffset, PtrOffset, TIL.AlignLog2});
788787

789788
Value *OffsetInRange = B.CreateICmpULE(BitOffset, TIL.SizeM1);
790789

@@ -1036,7 +1035,7 @@ LowerTypeTestsModule::importTypeId(StringRef TypeId) {
10361035
if (TIL.TheKind == TypeTestResolution::ByteArray ||
10371036
TIL.TheKind == TypeTestResolution::Inline ||
10381037
TIL.TheKind == TypeTestResolution::AllOnes) {
1039-
TIL.AlignLog2 = ImportConstant("align", TTRes.AlignLog2, 8, Int8Ty);
1038+
TIL.AlignLog2 = ImportConstant("align", TTRes.AlignLog2, 8, IntPtrTy);
10401039
TIL.SizeM1 =
10411040
ImportConstant("size_m1", TTRes.SizeM1, TTRes.SizeM1BitWidth, IntPtrTy);
10421041
}
@@ -1157,7 +1156,7 @@ void LowerTypeTestsModule::lowerTypeTestCalls(
11571156
TypeIdLowering TIL;
11581157
TIL.OffsetedGlobal = ConstantExpr::getGetElementPtr(
11591158
Int8Ty, CombinedGlobalAddr, ConstantInt::get(IntPtrTy, BSI.ByteOffset)),
1160-
TIL.AlignLog2 = ConstantInt::get(Int8Ty, BSI.AlignLog2);
1159+
TIL.AlignLog2 = ConstantInt::get(IntPtrTy, BSI.AlignLog2);
11611160
TIL.SizeM1 = ConstantInt::get(IntPtrTy, BSI.BitSize - 1);
11621161
if (BSI.isAllOnes()) {
11631162
TIL.TheKind = (BSI.BitSize == 1) ? TypeTestResolution::Single

‎llvm/test/ThinLTO/X86/cfi-devirt.ll‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -91,7 +91,7 @@ cont2:
9191
; CHECK-IR: br i1 {{.*}}, label %trap, label %cont2
9292

9393
; We still have to call it as virtual.
94-
; CHECK-IR: %call3 = tail call i32 %4
94+
; CHECK-IR: %call3 = tail call i32 %
9595
%call3 = tail call i32 %5(ptr nonnull %obj, i32 %call)
9696
ret i32 %call3
9797
}

‎llvm/test/Transforms/LowerTypeTests/export-allones.ll‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -142,11 +142,11 @@
142142
; CHECK: [[G:@[0-9]+]] = private constant { [2048 x i8] } zeroinitializer
143143

144144
; CHECK: @__typeid_typeid1_global_addr = hidden alias i8, ptr [[G]]
145-
; X86: @__typeid_typeid1_align = hidden alias i8, inttoptr (i8 1 to ptr)
145+
; X86: @__typeid_typeid1_align = hidden alias i8, inttoptr (i64 1 to ptr)
146146
; X86: @__typeid_typeid1_size_m1 = hidden alias i8, inttoptr (i64 1 to ptr)
147147

148148
; CHECK: @__typeid_typeid2_global_addr = hidden alias i8, getelementptr (i8, ptr [[G]], i64 4)
149-
; X86: @__typeid_typeid2_align = hidden alias i8, inttoptr (i8 2 to ptr)
149+
; X86: @__typeid_typeid2_align = hidden alias i8, inttoptr (i64 2 to ptr)
150150
; X86: @__typeid_typeid2_size_m1 = hidden alias i8, inttoptr (i64 128 to ptr)
151151

152152
; ARM-NOT: alias {{.*}} inttoptr

‎llvm/test/Transforms/LowerTypeTests/export-bytearray.ll‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -15,13 +15,13 @@
1515
; CHECK: [[B:@[0-9]+]] = private constant [258 x i8] c"\03\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\02\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\01"
1616

1717
; CHECK: @__typeid_typeid1_global_addr = hidden alias i8, ptr [[G]]
18-
; X86: @__typeid_typeid1_align = hidden alias i8, inttoptr (i8 1 to ptr)
18+
; X86: @__typeid_typeid1_align = hidden alias i8, inttoptr (i64 1 to ptr)
1919
; X86: @__typeid_typeid1_size_m1 = hidden alias i8, inttoptr (i64 65 to ptr)
2020
; CHECK: @__typeid_typeid1_byte_array = hidden alias i8, ptr @bits.1
2121
; X86: @__typeid_typeid1_bit_mask = hidden alias i8, inttoptr (i8 2 to ptr)
2222

2323
; CHECK: @__typeid_typeid2_global_addr = hidden alias i8, getelementptr (i8, ptr [[G]], i64 4)
24-
; X86: @__typeid_typeid2_align = hidden alias i8, inttoptr (i8 2 to ptr)
24+
; X86: @__typeid_typeid2_align = hidden alias i8, inttoptr (i64 2 to ptr)
2525
; X86: @__typeid_typeid2_size_m1 = hidden alias i8, inttoptr (i64 257 to ptr)
2626
; CHECK: @__typeid_typeid2_byte_array = hidden alias i8, ptr @bits
2727
; X86: @__typeid_typeid2_bit_mask = hidden alias i8, inttoptr (i8 1 to ptr)

‎llvm/test/Transforms/LowerTypeTests/export-icall.ll‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -37,7 +37,7 @@ define void @f3(i32 %x) !type !8 {
3737

3838

3939
; CHECK-DAG: @__typeid_typeid1_global_addr = hidden alias i8, ptr [[JT1:.*]]
40-
; CHECK-DAG: @__typeid_typeid1_align = hidden alias i8, inttoptr (i8 3 to ptr)
40+
; CHECK-DAG: @__typeid_typeid1_align = hidden alias i8, inttoptr (i64 3 to ptr)
4141
; CHECK-DAG: @__typeid_typeid1_size_m1 = hidden alias i8, inttoptr (i64 4 to ptr)
4242

4343
; CHECK-DAG: @h = alias void (i8), ptr [[JT1]]

‎llvm/test/Transforms/LowerTypeTests/import.ll‎

Lines changed: 26 additions & 32 deletions
Original file line numberDiff line numberDiff line change
@@ -37,8 +37,7 @@ define i1 @allones7(ptr %p) {
3737
; X86-SAME: ptr [[P:%.*]]) {
3838
; X86-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P]] to i64
3939
; X86-NEXT: [[TMP2:%.*]] = sub i64 [[TMP1]], ptrtoint (ptr @__typeid_allones7_global_addr to i64)
40-
; X86-NEXT: [[TMP3:%.*]] = zext i8 ptrtoint (ptr @__typeid_allones7_align to i8) to i64
41-
; X86-NEXT: [[TMP7:%.*]] = call i64 @llvm.fshr.i64(i64 [[TMP2]], i64 [[TMP2]], i64 [[TMP3]])
40+
; X86-NEXT: [[TMP7:%.*]] = call i64 @llvm.fshr.i64(i64 [[TMP2]], i64 [[TMP2]], i64 ptrtoint (ptr @__typeid_allones7_align to i64))
4241
; X86-NEXT: [[TMP8:%.*]] = icmp ule i64 [[TMP7]], ptrtoint (ptr @__typeid_allones7_size_m1 to i64)
4342
; X86-NEXT: ret i1 [[TMP8]]
4443
;
@@ -59,8 +58,7 @@ define i1 @allones32(ptr %p) {
5958
; X86-SAME: ptr [[P:%.*]]) {
6059
; X86-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P]] to i64
6160
; X86-NEXT: [[TMP2:%.*]] = sub i64 [[TMP1]], ptrtoint (ptr @__typeid_allones32_global_addr to i64)
62-
; X86-NEXT: [[TMP3:%.*]] = zext i8 ptrtoint (ptr @__typeid_allones32_align to i8) to i64
63-
; X86-NEXT: [[TMP7:%.*]] = call i64 @llvm.fshr.i64(i64 [[TMP2]], i64 [[TMP2]], i64 [[TMP3]])
61+
; X86-NEXT: [[TMP7:%.*]] = call i64 @llvm.fshr.i64(i64 [[TMP2]], i64 [[TMP2]], i64 ptrtoint (ptr @__typeid_allones32_align to i64))
6462
; X86-NEXT: [[TMP8:%.*]] = icmp ule i64 [[TMP7]], ptrtoint (ptr @__typeid_allones32_size_m1 to i64)
6563
; X86-NEXT: ret i1 [[TMP8]]
6664
;
@@ -81,18 +79,17 @@ define i1 @bytearray7(ptr %p) {
8179
; X86-SAME: ptr [[P:%.*]]) {
8280
; X86-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P]] to i64
8381
; X86-NEXT: [[TMP2:%.*]] = sub i64 [[TMP1]], ptrtoint (ptr @__typeid_bytearray7_global_addr to i64)
84-
; X86-NEXT: [[TMP3:%.*]] = zext i8 ptrtoint (ptr @__typeid_bytearray7_align to i8) to i64
85-
; X86-NEXT: [[TMP7:%.*]] = call i64 @llvm.fshr.i64(i64 [[TMP2]], i64 [[TMP2]], i64 [[TMP3]])
82+
; X86-NEXT: [[TMP7:%.*]] = call i64 @llvm.fshr.i64(i64 [[TMP2]], i64 [[TMP2]], i64 ptrtoint (ptr @__typeid_bytearray7_align to i64))
8683
; X86-NEXT: [[TMP8:%.*]] = icmp ule i64 [[TMP7]], ptrtoint (ptr @__typeid_bytearray7_size_m1 to i64)
87-
; X86-NEXT: br i1 [[TMP8]], label [[TMP9:%.*]], label [[TMP14:%.*]]
88-
; X86: 6:
84+
; X86-NEXT: br i1 [[TMP8]], label %[[TMP9:.*]], label %[[TMP14:.*]]
85+
; X86: [[TMP9]]:
8986
; X86-NEXT: [[TMP10:%.*]] = getelementptr i8, ptr @__typeid_bytearray7_byte_array, i64 [[TMP7]]
9087
; X86-NEXT: [[TMP11:%.*]] = load i8, ptr [[TMP10]], align 1
9188
; X86-NEXT: [[TMP12:%.*]] = and i8 [[TMP11]], ptrtoint (ptr @__typeid_bytearray7_bit_mask to i8)
9289
; X86-NEXT: [[TMP13:%.*]] = icmp ne i8 [[TMP12]], 0
93-
; X86-NEXT: br label [[TMP14]]
94-
; X86: 11:
95-
; X86-NEXT: [[TMP15:%.*]] = phi i1 [ false, [[TMP0:%.*]] ], [ [[TMP13]], [[TMP9]] ]
90+
; X86-NEXT: br label %[[TMP14]]
91+
; X86: [[TMP14]]:
92+
; X86-NEXT: [[TMP15:%.*]] = phi i1 [ false, [[TMP0:%.*]] ], [ [[TMP13]], %[[TMP9]] ]
9693
; X86-NEXT: ret i1 [[TMP15]]
9794
;
9895
; ARM-LABEL: define i1 @bytearray7(
@@ -121,18 +118,17 @@ define i1 @bytearray32(ptr %p) {
121118
; X86-SAME: ptr [[P:%.*]]) {
122119
; X86-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P]] to i64
123120
; X86-NEXT: [[TMP2:%.*]] = sub i64 [[TMP1]], ptrtoint (ptr @__typeid_bytearray32_global_addr to i64)
124-
; X86-NEXT: [[TMP3:%.*]] = zext i8 ptrtoint (ptr @__typeid_bytearray32_align to i8) to i64
125-
; X86-NEXT: [[TMP7:%.*]] = call i64 @llvm.fshr.i64(i64 [[TMP2]], i64 [[TMP2]], i64 [[TMP3]])
121+
; X86-NEXT: [[TMP7:%.*]] = call i64 @llvm.fshr.i64(i64 [[TMP2]], i64 [[TMP2]], i64 ptrtoint (ptr @__typeid_bytearray32_align to i64))
126122
; X86-NEXT: [[TMP8:%.*]] = icmp ule i64 [[TMP7]], ptrtoint (ptr @__typeid_bytearray32_size_m1 to i64)
127-
; X86-NEXT: br i1 [[TMP8]], label [[TMP9:%.*]], label [[TMP14:%.*]]
128-
; X86: 6:
123+
; X86-NEXT: br i1 [[TMP8]], label %[[TMP9:.*]], label %[[TMP14:.*]]
124+
; X86: [[TMP9]]:
129125
; X86-NEXT: [[TMP10:%.*]] = getelementptr i8, ptr @__typeid_bytearray32_byte_array, i64 [[TMP7]]
130126
; X86-NEXT: [[TMP11:%.*]] = load i8, ptr [[TMP10]], align 1
131127
; X86-NEXT: [[TMP12:%.*]] = and i8 [[TMP11]], ptrtoint (ptr @__typeid_bytearray32_bit_mask to i8)
132128
; X86-NEXT: [[TMP13:%.*]] = icmp ne i8 [[TMP12]], 0
133-
; X86-NEXT: br label [[TMP14]]
134-
; X86: 11:
135-
; X86-NEXT: [[TMP15:%.*]] = phi i1 [ false, [[TMP0:%.*]] ], [ [[TMP13]], [[TMP9]] ]
129+
; X86-NEXT: br label %[[TMP14]]
130+
; X86: [[TMP14]]:
131+
; X86-NEXT: [[TMP15:%.*]] = phi i1 [ false, [[TMP0:%.*]] ], [ [[TMP13]], %[[TMP9]] ]
136132
; X86-NEXT: ret i1 [[TMP15]]
137133
;
138134
; ARM-LABEL: define i1 @bytearray32(
@@ -161,19 +157,18 @@ define i1 @inline5(ptr %p) {
161157
; X86-SAME: ptr [[P:%.*]]) {
162158
; X86-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P]] to i64
163159
; X86-NEXT: [[TMP2:%.*]] = sub i64 [[TMP1]], ptrtoint (ptr @__typeid_inline5_global_addr to i64)
164-
; X86-NEXT: [[TMP3:%.*]] = zext i8 ptrtoint (ptr @__typeid_inline5_align to i8) to i64
165-
; X86-NEXT: [[TMP7:%.*]] = call i64 @llvm.fshr.i64(i64 [[TMP2]], i64 [[TMP2]], i64 [[TMP3]])
160+
; X86-NEXT: [[TMP7:%.*]] = call i64 @llvm.fshr.i64(i64 [[TMP2]], i64 [[TMP2]], i64 ptrtoint (ptr @__typeid_inline5_align to i64))
166161
; X86-NEXT: [[TMP8:%.*]] = icmp ule i64 [[TMP7]], ptrtoint (ptr @__typeid_inline5_size_m1 to i64)
167-
; X86-NEXT: br i1 [[TMP8]], label [[TMP9:%.*]], label [[TMP15:%.*]]
168-
; X86: 6:
162+
; X86-NEXT: br i1 [[TMP8]], label %[[TMP9:.*]], label %[[TMP15:.*]]
163+
; X86: [[TMP9]]:
169164
; X86-NEXT: [[TMP10:%.*]] = trunc i64 [[TMP7]] to i32
170165
; X86-NEXT: [[TMP11:%.*]] = and i32 [[TMP10]], 31
171166
; X86-NEXT: [[TMP12:%.*]] = shl i32 1, [[TMP11]]
172167
; X86-NEXT: [[TMP13:%.*]] = and i32 ptrtoint (ptr @__typeid_inline5_inline_bits to i32), [[TMP12]]
173168
; X86-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
174-
; X86-NEXT: br label [[TMP15]]
175-
; X86: 12:
176-
; X86-NEXT: [[TMP16:%.*]] = phi i1 [ false, [[TMP0:%.*]] ], [ [[TMP14]], [[TMP9]] ]
169+
; X86-NEXT: br label %[[TMP15]]
170+
; X86: [[TMP15]]:
171+
; X86-NEXT: [[TMP16:%.*]] = phi i1 [ false, [[TMP0:%.*]] ], [ [[TMP14]], %[[TMP9]] ]
177172
; X86-NEXT: ret i1 [[TMP16]]
178173
;
179174
; ARM-LABEL: define i1 @inline5(
@@ -203,18 +198,17 @@ define i1 @inline6(ptr %p) {
203198
; X86-SAME: ptr [[P:%.*]]) {
204199
; X86-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P]] to i64
205200
; X86-NEXT: [[TMP2:%.*]] = sub i64 [[TMP1]], ptrtoint (ptr @__typeid_inline6_global_addr to i64)
206-
; X86-NEXT: [[TMP3:%.*]] = zext i8 ptrtoint (ptr @__typeid_inline6_align to i8) to i64
207-
; X86-NEXT: [[TMP7:%.*]] = call i64 @llvm.fshr.i64(i64 [[TMP2]], i64 [[TMP2]], i64 [[TMP3]])
201+
; X86-NEXT: [[TMP7:%.*]] = call i64 @llvm.fshr.i64(i64 [[TMP2]], i64 [[TMP2]], i64 ptrtoint (ptr @__typeid_inline6_align to i64))
208202
; X86-NEXT: [[TMP8:%.*]] = icmp ule i64 [[TMP7]], ptrtoint (ptr @__typeid_inline6_size_m1 to i64)
209-
; X86-NEXT: br i1 [[TMP8]], label [[TMP9:%.*]], label [[TMP14:%.*]]
210-
; X86: 6:
203+
; X86-NEXT: br i1 [[TMP8]], label %[[TMP9:.*]], label %[[TMP14:.*]]
204+
; X86: [[TMP9]]:
211205
; X86-NEXT: [[TMP10:%.*]] = and i64 [[TMP7]], 63
212206
; X86-NEXT: [[TMP11:%.*]] = shl i64 1, [[TMP10]]
213207
; X86-NEXT: [[TMP12:%.*]] = and i64 ptrtoint (ptr @__typeid_inline6_inline_bits to i64), [[TMP11]]
214208
; X86-NEXT: [[TMP13:%.*]] = icmp ne i64 [[TMP12]], 0
215-
; X86-NEXT: br label [[TMP14]]
216-
; X86: 11:
217-
; X86-NEXT: [[TMP15:%.*]] = phi i1 [ false, [[TMP0:%.*]] ], [ [[TMP13]], [[TMP9]] ]
209+
; X86-NEXT: br label %[[TMP14]]
210+
; X86: [[TMP14]]:
211+
; X86-NEXT: [[TMP15:%.*]] = phi i1 [ false, [[TMP0:%.*]] ], [ [[TMP13]], %[[TMP9]] ]
218212
; X86-NEXT: ret i1 [[TMP15]]
219213
;
220214
; ARM-LABEL: define i1 @inline6(

‎llvm/test/Transforms/LowerTypeTests/simplify.ll‎

Lines changed: 6 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -11,19 +11,18 @@ define i1 @bytearray7(ptr %p) {
1111
; CHECK-SAME: ptr [[P:%.*]]) {
1212
; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P]] to i64
1313
; CHECK-NEXT: [[TMP2:%.*]] = sub i64 [[TMP1]], ptrtoint (ptr @__typeid_bytearray7_global_addr to i64)
14-
; CHECK-NEXT: [[TMP3:%.*]] = zext i8 ptrtoint (ptr @__typeid_bytearray7_align to i8) to i64
15-
; CHECK-NEXT: [[TMP7:%.*]] = call i64 @llvm.fshr.i64(i64 [[TMP2]], i64 [[TMP2]], i64 [[TMP3]])
14+
; CHECK-NEXT: [[TMP7:%.*]] = call i64 @llvm.fshr.i64(i64 [[TMP2]], i64 [[TMP2]], i64 ptrtoint (ptr @__typeid_bytearray7_align to i64))
1615
; CHECK-NEXT: [[TMP8:%.*]] = icmp ule i64 [[TMP7]], ptrtoint (ptr @__typeid_bytearray7_size_m1 to i64)
17-
; CHECK-NEXT: br i1 [[TMP8]], label [[TMP9:%.*]], label [[F:%.*]]
18-
; CHECK: 6:
16+
; CHECK-NEXT: br i1 [[TMP8]], label %[[TMP9:.*]], label %[[F:.*]]
17+
; CHECK: [[TMP9]]:
1918
; CHECK-NEXT: [[TMP10:%.*]] = getelementptr i8, ptr @__typeid_bytearray7_byte_array, i64 [[TMP7]]
2019
; CHECK-NEXT: [[TMP11:%.*]] = load i8, ptr [[TMP10]], align 1
2120
; CHECK-NEXT: [[TMP12:%.*]] = and i8 [[TMP11]], ptrtoint (ptr @__typeid_bytearray7_bit_mask to i8)
2221
; CHECK-NEXT: [[TMP13:%.*]] = icmp ne i8 [[TMP12]], 0
23-
; CHECK-NEXT: br i1 [[TMP13]], label [[T:%.*]], label [[F]]
24-
; CHECK: t:
22+
; CHECK-NEXT: br i1 [[TMP13]], label %[[T:.*]], label %[[F]]
23+
; CHECK: [[T]]:
2524
; CHECK-NEXT: ret i1 true
26-
; CHECK: f:
25+
; CHECK: [[F]]:
2726
; CHECK-NEXT: ret i1 false
2827
;
2928
%x = call i1 @llvm.type.test(ptr %p, metadata !"bytearray7")

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