3434 %a.lane.0 = fmul double %v1.lane.0 , %v2.lane.2
3535 %a.lane.1 = fmul double %v1.lane.1 , %v2.lane.3
3636
37- %a.ins.0 = insertelement <2 x double > undef , double %a.lane.0 , i32 0
37+ %a.ins.0 = insertelement <2 x double > zeroinitializer , double %a.lane.0 , i32 0
3838 %a.ins.1 = insertelement <2 x double > %a.ins.0 , double %a.lane.1 , i32 1
3939
4040 call void @use (double %v1.lane.0 )
7373 %a.lane.0 = fmul double %v1.lane.0 , %v2.lane.2
7474 %a.lane.1 = fmul double %v3.lane.1 , %v2.lane.2
7575
76- %a.ins.0 = insertelement <2 x double > undef , double %a.lane.0 , i32 0
76+ %a.ins.0 = insertelement <2 x double > zeroinitializer , double %a.lane.0 , i32 0
7777 %a.ins.1 = insertelement <2 x double > %a.ins.0 , double %a.lane.1 , i32 1
7878
7979 call void @use (double %v1.lane.0 )
@@ -95,7 +95,8 @@ define void @noop_extract_second_2_lanes(ptr %ptr.1, ptr %ptr.2) {
9595; CHECK-NEXT: [[TMP0:%.*]] = shufflevector <4 x double> [[V_1]], <4 x double> poison, <2 x i32> <i32 2, i32 3>
9696; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x double> [[V_2]], <4 x double> poison, <2 x i32> <i32 2, i32 2>
9797; CHECK-NEXT: [[TMP2:%.*]] = fmul <2 x double> [[TMP0]], [[TMP1]]
98- ; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <2 x double> [[TMP2]], <2 x double> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
98+ ; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <2 x double> [[TMP2]], <2 x double> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
99+ ; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <4 x double> zeroinitializer, <4 x double> [[TMP4]], <4 x i32> <i32 4, i32 5, i32 2, i32 3>
99100; CHECK-NEXT: call void @use(double [[V1_LANE_2]])
100101; CHECK-NEXT: call void @use(double [[V1_LANE_3]])
101102; CHECK-NEXT: store <4 x double> [[TMP3]], ptr [[PTR_1]], align 8
112113 %a.lane.0 = fmul double %v1.lane.2 , %v2.lane.2
113114 %a.lane.1 = fmul double %v1.lane.3 , %v2.lane.2
114115
115- %a.ins.0 = insertelement <4 x double > undef , double %a.lane.0 , i32 0
116+ %a.ins.0 = insertelement <4 x double > zeroinitializer , double %a.lane.0 , i32 0
116117 %a.ins.1 = insertelement <4 x double > %a.ins.0 , double %a.lane.1 , i32 1
117118
118119 call void @use (double %v1.lane.2 )
149150 %a.lane.0 = fmul double %v1.lane.1 , %v2.lane.2
150151 %a.lane.1 = fmul double %v1.lane.0 , %v2.lane.2
151152
152- %a.ins.0 = insertelement <2 x double > undef , double %a.lane.0 , i32 0
153+ %a.ins.0 = insertelement <2 x double > zeroinitializer , double %a.lane.0 , i32 0
153154 %a.ins.1 = insertelement <2 x double > %a.ins.0 , double %a.lane.1 , i32 1
154155
155156 call void @use (double %v1.lane.0 )
@@ -170,7 +171,8 @@ define void @extract_lanes_1_and_2(ptr %ptr.1, ptr %ptr.2) {
170171; CHECK-NEXT: [[TMP0:%.*]] = shufflevector <4 x double> [[V_1]], <4 x double> poison, <2 x i32> <i32 1, i32 2>
171172; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x double> [[V_2]], <4 x double> poison, <2 x i32> <i32 2, i32 2>
172173; CHECK-NEXT: [[TMP2:%.*]] = fmul <2 x double> [[TMP0]], [[TMP1]]
173- ; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <2 x double> [[TMP2]], <2 x double> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
174+ ; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <2 x double> [[TMP2]], <2 x double> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
175+ ; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <4 x double> zeroinitializer, <4 x double> [[TMP4]], <4 x i32> <i32 4, i32 5, i32 2, i32 3>
174176; CHECK-NEXT: call void @use(double [[V1_LANE_1]])
175177; CHECK-NEXT: call void @use(double [[V1_LANE_2]])
176178; CHECK-NEXT: store <4 x double> [[TMP3]], ptr [[PTR_1]], align 8
187189 %a.lane.0 = fmul double %v1.lane.1 , %v2.lane.2
188190 %a.lane.1 = fmul double %v1.lane.2 , %v2.lane.2
189191
190- %a.ins.0 = insertelement <4 x double > undef , double %a.lane.0 , i32 0
192+ %a.ins.0 = insertelement <4 x double > zeroinitializer , double %a.lane.0 , i32 0
191193 %a.ins.1 = insertelement <4 x double > %a.ins.0 , double %a.lane.1 , i32 1
192194
193195 call void @use (double %v1.lane.1 )
@@ -213,7 +215,8 @@ define void @noop_extracts_existing_vector_4_lanes(ptr %ptr.1, ptr %ptr.2) {
213215; CHECK-NEXT: [[TMP0:%.*]] = shufflevector <9 x double> [[V_1]], <9 x double> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
214216; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x double> [[V_2]], <4 x double> poison, <4 x i32> <i32 2, i32 0, i32 2, i32 2>
215217; CHECK-NEXT: [[TMP2:%.*]] = fmul <4 x double> [[TMP0]], [[TMP1]]
216- ; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <4 x double> [[TMP2]], <4 x double> undef, <9 x i32> <i32 2, i32 3, i32 0, i32 1, i32 4, i32 5, i32 6, i32 7, i32 7>
218+ ; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <4 x double> [[TMP2]], <4 x double> poison, <9 x i32> <i32 2, i32 3, i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
219+ ; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <9 x double> zeroinitializer, <9 x double> [[TMP4]], <9 x i32> <i32 9, i32 10, i32 11, i32 12, i32 4, i32 5, i32 6, i32 7, i32 8>
217220; CHECK-NEXT: call void @use(double [[V1_LANE_0]])
218221; CHECK-NEXT: call void @use(double [[V1_LANE_1]])
219222; CHECK-NEXT: call void @use(double [[V1_LANE_2]])
235238 %a.lane.1 = fmul double %v1.lane.3 , %v2.lane.2
236239 %a.lane.2 = fmul double %v1.lane.0 , %v2.lane.2
237240 %a.lane.3 = fmul double %v1.lane.1 , %v2.lane.0
238- %a.ins.0 = insertelement <9 x double > undef , double %a.lane.0 , i32 0
241+ %a.ins.0 = insertelement <9 x double > zeroinitializer , double %a.lane.0 , i32 0
239242 %a.ins.1 = insertelement <9 x double > %a.ins.0 , double %a.lane.1 , i32 1
240243 %a.ins.2 = insertelement <9 x double > %a.ins.1 , double %a.lane.2 , i32 2
241244 %a.ins.3 = insertelement <9 x double > %a.ins.2 , double %a.lane.3 , i32 3
@@ -261,7 +264,8 @@ define void @extracts_jumbled_4_lanes(ptr %ptr.1, ptr %ptr.2) {
261264; CHECK-NEXT: [[TMP0:%.*]] = shufflevector <9 x double> [[V_1]], <9 x double> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
262265; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x double> [[V_2]], <4 x double> poison, <4 x i32> <i32 2, i32 2, i32 1, i32 0>
263266; CHECK-NEXT: [[TMP2:%.*]] = fmul <4 x double> [[TMP0]], [[TMP1]]
264- ; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <4 x double> [[TMP2]], <4 x double> undef, <9 x i32> <i32 0, i32 2, i32 1, i32 3, i32 4, i32 5, i32 6, i32 7, i32 7>
267+ ; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <4 x double> [[TMP2]], <4 x double> poison, <9 x i32> <i32 0, i32 2, i32 1, i32 3, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
268+ ; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <9 x double> zeroinitializer, <9 x double> [[TMP4]], <9 x i32> <i32 9, i32 10, i32 11, i32 12, i32 4, i32 5, i32 6, i32 7, i32 8>
265269; CHECK-NEXT: call void @use(double [[V1_LANE_0]])
266270; CHECK-NEXT: call void @use(double [[V1_LANE_1]])
267271; CHECK-NEXT: call void @use(double [[V1_LANE_2]])
283287 %a.lane.1 = fmul double %v1.lane.2 , %v2.lane.1
284288 %a.lane.2 = fmul double %v1.lane.1 , %v2.lane.2
285289 %a.lane.3 = fmul double %v1.lane.3 , %v2.lane.0
286- %a.ins.0 = insertelement <9 x double > undef , double %a.lane.0 , i32 0
290+ %a.ins.0 = insertelement <9 x double > zeroinitializer , double %a.lane.0 , i32 0
287291 %a.ins.1 = insertelement <9 x double > %a.ins.0 , double %a.lane.1 , i32 1
288292 %a.ins.2 = insertelement <9 x double > %a.ins.1 , double %a.lane.2 , i32 2
289293 %a.ins.3 = insertelement <9 x double > %a.ins.2 , double %a.lane.3 , i32 3
@@ -313,12 +317,14 @@ define void @noop_extracts_9_lanes(ptr %ptr.1, ptr %ptr.2) {
313317; CHECK-NEXT: [[TMP2:%.*]] = fmul <8 x double> [[TMP0]], [[TMP1]]
314318; CHECK-NEXT: [[A_LANE_8:%.*]] = fmul double [[V1_LANE_2]], [[V2_LANE_0]]
315319; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <8 x double> [[TMP2]], <8 x double> poison, <9 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 poison>
316- ; CHECK-NEXT: [[A_INS_8:%.*]] = insertelement <9 x double> [[TMP3]], double [[A_LANE_8]], i32 8
320+ ; CHECK-NEXT: [[A_INS_72:%.*]] = shufflevector <9 x double> zeroinitializer, <9 x double> [[TMP3]], <9 x i32> <i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 8>
321+ ; CHECK-NEXT: [[A_INS_8:%.*]] = insertelement <9 x double> [[A_INS_72]], double [[A_LANE_8]], i32 8
317322; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <9 x double> [[V_1]], <9 x double> poison, <8 x i32> <i32 6, i32 7, i32 8, i32 0, i32 1, i32 2, i32 3, i32 4>
318323; CHECK-NEXT: [[TMP6:%.*]] = fmul <8 x double> [[TMP4]], [[TMP5]]
319324; CHECK-NEXT: [[B_LANE_8:%.*]] = fmul double [[V1_LANE_5]], [[V2_LANE_0]]
320325; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <8 x double> [[TMP6]], <8 x double> poison, <9 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 poison>
321- ; CHECK-NEXT: [[B_INS_8:%.*]] = insertelement <9 x double> [[TMP7]], double [[B_LANE_8]], i32 8
326+ ; CHECK-NEXT: [[B_INS_71:%.*]] = shufflevector <9 x double> zeroinitializer, <9 x double> [[TMP7]], <9 x i32> <i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 8>
327+ ; CHECK-NEXT: [[B_INS_8:%.*]] = insertelement <9 x double> [[B_INS_71]], double [[B_LANE_8]], i32 8
322328; CHECK-NEXT: [[RES:%.*]] = fsub <9 x double> [[A_INS_8]], [[B_INS_8]]
323329; CHECK-NEXT: store <9 x double> [[RES]], ptr [[PTR_1]], align 8
324330; CHECK-NEXT: ret void
350356 %a.lane.7 = fmul double %v1.lane.1 , %v2.lane.1
351357 %a.lane.8 = fmul double %v1.lane.2 , %v2.lane.0
352358
353- %a.ins.0 = insertelement <9 x double > undef , double %a.lane.0 , i32 0
359+ %a.ins.0 = insertelement <9 x double > zeroinitializer , double %a.lane.0 , i32 0
354360 %a.ins.1 = insertelement <9 x double > %a.ins.0 , double %a.lane.1 , i32 1
355361 %a.ins.2 = insertelement <9 x double > %a.ins.1 , double %a.lane.2 , i32 2
356362 %a.ins.3 = insertelement <9 x double > %a.ins.2 , double %a.lane.3 , i32 3
370376 %b.lane.7 = fmul double %v1.lane.4 , %v2.lane.1
371377 %b.lane.8 = fmul double %v1.lane.5 , %v2.lane.0
372378
373- %b.ins.0 = insertelement <9 x double > undef , double %b.lane.0 , i32 0
379+ %b.ins.0 = insertelement <9 x double > zeroinitializer , double %b.lane.0 , i32 0
374380 %b.ins.1 = insertelement <9 x double > %b.ins.0 , double %b.lane.1 , i32 1
375381 %b.ins.2 = insertelement <9 x double > %b.ins.1 , double %b.lane.2 , i32 2
376382 %b.ins.3 = insertelement <9 x double > %b.ins.2 , double %b.lane.3 , i32 3
@@ -401,12 +407,14 @@ define void @first_mul_chain_jumbled(ptr %ptr.1, ptr %ptr.2) {
401407; CHECK-NEXT: [[V2_LANE_1:%.*]] = extractelement <4 x double> [[V_2]], i32 1
402408; CHECK-NEXT: [[A_LANE_8:%.*]] = fmul double [[V1_LANE_2]], [[V2_LANE_1]]
403409; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <8 x double> [[TMP2]], <8 x double> poison, <9 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 poison>
404- ; CHECK-NEXT: [[A_INS_8:%.*]] = insertelement <9 x double> [[TMP3]], double [[A_LANE_8]], i32 8
410+ ; CHECK-NEXT: [[A_INS_72:%.*]] = shufflevector <9 x double> zeroinitializer, <9 x double> [[TMP3]], <9 x i32> <i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 8>
411+ ; CHECK-NEXT: [[A_INS_8:%.*]] = insertelement <9 x double> [[A_INS_72]], double [[A_LANE_8]], i32 8
405412; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <9 x double> [[V_1]], <9 x double> poison, <8 x i32> <i32 6, i32 7, i32 8, i32 0, i32 1, i32 2, i32 3, i32 4>
406413; CHECK-NEXT: [[TMP5:%.*]] = fmul <8 x double> [[TMP4]], [[TMP1]]
407414; CHECK-NEXT: [[B_LANE_8:%.*]] = fmul double [[V1_LANE_5]], [[V2_LANE_0]]
408415; CHECK-NEXT: [[TMP6:%.*]] = shufflevector <8 x double> [[TMP5]], <8 x double> poison, <9 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 poison>
409- ; CHECK-NEXT: [[B_INS_8:%.*]] = insertelement <9 x double> [[TMP6]], double [[B_LANE_8]], i32 8
416+ ; CHECK-NEXT: [[B_INS_71:%.*]] = shufflevector <9 x double> zeroinitializer, <9 x double> [[TMP6]], <9 x i32> <i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 8>
417+ ; CHECK-NEXT: [[B_INS_8:%.*]] = insertelement <9 x double> [[B_INS_71]], double [[B_LANE_8]], i32 8
410418; CHECK-NEXT: [[RES:%.*]] = fsub <9 x double> [[A_INS_8]], [[B_INS_8]]
411419; CHECK-NEXT: store <9 x double> [[RES]], ptr [[PTR_1]], align 8
412420; CHECK-NEXT: ret void
438446 %a.lane.7 = fmul double %v1.lane.0 , %v2.lane.2
439447 %a.lane.8 = fmul double %v1.lane.2 , %v2.lane.1
440448
441- %a.ins.0 = insertelement <9 x double > undef , double %a.lane.0 , i32 0
449+ %a.ins.0 = insertelement <9 x double > zeroinitializer , double %a.lane.0 , i32 0
442450 %a.ins.1 = insertelement <9 x double > %a.ins.0 , double %a.lane.1 , i32 1
443451 %a.ins.2 = insertelement <9 x double > %a.ins.1 , double %a.lane.2 , i32 2
444452 %a.ins.3 = insertelement <9 x double > %a.ins.2 , double %a.lane.3 , i32 3
458466 %b.lane.7 = fmul double %v1.lane.4 , %v2.lane.2
459467 %b.lane.8 = fmul double %v1.lane.5 , %v2.lane.0
460468
461- %b.ins.0 = insertelement <9 x double > undef , double %b.lane.0 , i32 0
469+ %b.ins.0 = insertelement <9 x double > zeroinitializer , double %b.lane.0 , i32 0
462470 %b.ins.1 = insertelement <9 x double > %b.ins.0 , double %b.lane.1 , i32 1
463471 %b.ins.2 = insertelement <9 x double > %b.ins.1 , double %b.lane.2 , i32 2
464472 %b.ins.3 = insertelement <9 x double > %b.ins.2 , double %b.lane.3 , i32 3
@@ -490,12 +498,14 @@ define void @first_and_second_mul_chain_jumbled(ptr %ptr.1, ptr %ptr.2) {
490498; CHECK-NEXT: [[TMP2:%.*]] = fmul <8 x double> [[TMP0]], [[TMP1]]
491499; CHECK-NEXT: [[A_LANE_8:%.*]] = fmul double [[V1_LANE_2]], [[V2_LANE_0]]
492500; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <8 x double> [[TMP2]], <8 x double> poison, <9 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 poison>
493- ; CHECK-NEXT: [[A_INS_8:%.*]] = insertelement <9 x double> [[TMP3]], double [[A_LANE_8]], i32 8
501+ ; CHECK-NEXT: [[A_INS_72:%.*]] = shufflevector <9 x double> zeroinitializer, <9 x double> [[TMP3]], <9 x i32> <i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 8>
502+ ; CHECK-NEXT: [[A_INS_8:%.*]] = insertelement <9 x double> [[A_INS_72]], double [[A_LANE_8]], i32 8
494503; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <9 x double> [[V_1]], <9 x double> poison, <8 x i32> <i32 7, i32 6, i32 8, i32 1, i32 0, i32 3, i32 2, i32 5>
495504; CHECK-NEXT: [[TMP6:%.*]] = fmul <8 x double> [[TMP4]], [[TMP5]]
496505; CHECK-NEXT: [[B_LANE_8:%.*]] = fmul double [[V1_LANE_4]], [[V2_LANE_2]]
497506; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <8 x double> [[TMP6]], <8 x double> poison, <9 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 poison>
498- ; CHECK-NEXT: [[B_INS_8:%.*]] = insertelement <9 x double> [[TMP7]], double [[B_LANE_8]], i32 8
507+ ; CHECK-NEXT: [[B_INS_71:%.*]] = shufflevector <9 x double> zeroinitializer, <9 x double> [[TMP7]], <9 x i32> <i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 8>
508+ ; CHECK-NEXT: [[B_INS_8:%.*]] = insertelement <9 x double> [[B_INS_71]], double [[B_LANE_8]], i32 8
499509; CHECK-NEXT: [[RES:%.*]] = fsub <9 x double> [[A_INS_8]], [[B_INS_8]]
500510; CHECK-NEXT: store <9 x double> [[RES]], ptr [[PTR_1]], align 8
501511; CHECK-NEXT: ret void
527537 %a.lane.7 = fmul double %v1.lane.0 , %v2.lane.1
528538 %a.lane.8 = fmul double %v1.lane.2 , %v2.lane.0
529539
530- %a.ins.0 = insertelement <9 x double > undef , double %a.lane.0 , i32 0
540+ %a.ins.0 = insertelement <9 x double > zeroinitializer , double %a.lane.0 , i32 0
531541 %a.ins.1 = insertelement <9 x double > %a.ins.0 , double %a.lane.1 , i32 1
532542 %a.ins.2 = insertelement <9 x double > %a.ins.1 , double %a.lane.2 , i32 2
533543 %a.ins.3 = insertelement <9 x double > %a.ins.2 , double %a.lane.3 , i32 3
547557 %b.lane.7 = fmul double %v1.lane.5 , %v2.lane.0
548558 %b.lane.8 = fmul double %v1.lane.4 , %v2.lane.2
549559
550- %b.ins.0 = insertelement <9 x double > undef , double %b.lane.0 , i32 0
560+ %b.ins.0 = insertelement <9 x double > zeroinitializer , double %b.lane.0 , i32 0
551561 %b.ins.1 = insertelement <9 x double > %b.ins.0 , double %b.lane.1 , i32 1
552562 %b.ins.2 = insertelement <9 x double > %b.ins.1 , double %b.lane.2 , i32 2
553563 %b.ins.3 = insertelement <9 x double > %b.ins.2 , double %b.lane.3 , i32 3
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