Remove performance counters initial support

Dmitry Bushev · AnastasiyaChernikova · commit 106756a24642 · 2024-10-30T23:59:35.000+03:00
diff --git a/llvm/lib/Target/RISCV/CMakeLists.txt b/llvm/lib/Target/RISCV/CMakeLists.txt
@@ -15,7 +15,6 @@ tablegen(LLVM RISCVGenRegisterBank.inc -gen-register-bank)
 tablegen(LLVM RISCVGenRegisterInfo.inc -gen-register-info)
 tablegen(LLVM RISCVGenSearchableTables.inc -gen-searchable-tables)
 tablegen(LLVM RISCVGenSubtargetInfo.inc -gen-subtarget)
-tablegen(LLVM RISCVGenExegesis.inc -gen-exegesis)
 
 set(LLVM_TARGET_DEFINITIONS RISCVGISel.td)
 tablegen(LLVM RISCVGenGlobalISel.inc -gen-global-isel)
diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td
@@ -84,9 +84,3 @@ def RISCV : Target {
   let AssemblyWriters = [RISCVAsmWriter];
   let AllowRegisterRenaming = 1;
 }
-
-//===----------------------------------------------------------------------===//
-// Pfm Counters
-//===----------------------------------------------------------------------===//
-
-include "RISCVPfmCounters.td"
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -526,7 +526,7 @@ class BranchCC_rri<bits<3> funct3, string opcodestr>
   let isTerminator = 1;
 }
 
-let hasSideEffects = 0, mayLoad = 1, mayStore = 0, UseNamedOperandTable = 1 in {
+let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
 class Load_ri<bits<3> funct3, string opcodestr, DAGOperand rty = GPR>
     : RVInstI<funct3, OPC_LOAD, (outs rty:$rd), (ins GPRMem:$rs1, simm12:$imm12),
               opcodestr, "$rd, ${imm12}(${rs1})">;
@@ -541,7 +541,7 @@ class HLoad_r<bits<7> funct7, bits<5> funct5, string opcodestr>
 // Operands for stores are in the order srcreg, base, offset rather than
 // reflecting the order these fields are specified in the instruction
 // encoding.
-let hasSideEffects = 0, mayLoad = 0, mayStore = 1, UseNamedOperandTable = 1 in {
+let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in {
 class Store_rri<bits<3> funct3, string opcodestr, DAGOperand rty = GPR>
     : RVInstS<funct3, OPC_STORE, (outs),
               (ins rty:$rs2, GPRMem:$rs1, simm12:$imm12),
diff --git a/llvm/lib/Target/RISCV/RISCVPfmCounters.td b/llvm/lib/Target/RISCV/RISCVPfmCounters.td
diff --git a/llvm/tools/llvm-exegesis/lib/RISCV/CMakeLists.txt b/llvm/tools/llvm-exegesis/lib/RISCV/CMakeLists.txt
@@ -15,7 +15,6 @@ add_llvm_library(LLVMExegesisRISCV
   DISABLE_LLVM_LINK_LLVM_DYLIB
   STATIC
   Target.cpp
-  RISCVCounters.cpp
 
   DEPENDS
   intrinsics_gen
diff --git a/llvm/tools/llvm-exegesis/lib/RISCV/RISCVCounters.cpp b/llvm/tools/llvm-exegesis/lib/RISCV/RISCVCounters.cpp
diff --git a/llvm/tools/llvm-exegesis/lib/RISCV/RISCVCounters.h b/llvm/tools/llvm-exegesis/lib/RISCV/RISCVCounters.h
diff --git a/llvm/tools/llvm-exegesis/lib/RISCV/Target.cpp b/llvm/tools/llvm-exegesis/lib/RISCV/Target.cpp
@@ -8,8 +8,6 @@
 
 #include "../Target.h"
 
-#include "RISCVCounters.h"
-
 #include "MCTargetDesc/RISCVBaseInfo.h"
 #include "MCTargetDesc/RISCVMCTargetDesc.h"
 #include "MCTargetDesc/RISCVMatInt.h"
@@ -31,17 +29,10 @@ namespace exegesis {
 
 namespace {
 
-#include "RISCVGenExegesis.inc"
-
 class ExegesisRISCVTarget : public ExegesisTarget {
 public:
   ExegesisRISCVTarget();
 
-  Expected<std::unique_ptr<pfm::CounterGroup>>
-  createCounter(StringRef CounterName, const LLVMState &State,
-                ArrayRef<const char *> ValidationCounters,
-                const pid_t ProcessID) const override;
-
   bool checkOpcodeSupported(int Opcode,
                             const MCSubtargetInfo &SI) const override;
 
@@ -81,19 +72,8 @@ class ExegesisRISCVTarget : public ExegesisTarget {
 };
 
 ExegesisRISCVTarget::ExegesisRISCVTarget()
-    : ExegesisTarget(RISCVCpuPfmCounters, RISCV_MC::isOpcodeAvailable) {}
-
-Expected<std::unique_ptr<pfm::CounterGroup>> ExegesisRISCVTarget::createCounter(
-    StringRef CounterName, const LLVMState &State,
-    ArrayRef<const char *> ValidationCounters, const pid_t ProcessID) const {
-  if (CounterName == RISCVPfmCounterNames[0]) {
-    // TODO add support for Linux perf counters
-    return createRISCVCpuCyclesCounter(pfm::PerfEvent(CounterName));
-  }
-  return make_error<Failure>(Twine("Unsupported performance counter '")
-                                 .concat(CounterName)
-                                 .concat("'"));
-}
+    : ExegesisTarget(ArrayRef<CpuAndPfmCounters>{},
+                     RISCV_MC::isOpcodeAvailable) {}
 
 bool ExegesisRISCVTarget::checkOpcodeSupported(
     int Opcode, const MCSubtargetInfo &SI) const {
@@ -135,11 +115,12 @@ static std::vector<MCInst> loadIntReg(const MCSubtargetInfo &STI, unsigned Reg,
   for (const RISCVMatInt::Inst &Inst : InstSeq) {
     switch (Inst.getOpndKind()) {
     case RISCVMatInt::Imm:
-      MatIntInstrs.push_back(
-          MCInstBuilder(RISCV::LUI).addReg(DestReg).addImm(Inst.getImm()));
+      MatIntInstrs.push_back(MCInstBuilder(Inst.getOpcode())
+                                 .addReg(DestReg)
+                                 .addImm(Inst.getImm()));
       break;
     case RISCVMatInt::RegX0:
-      MatIntInstrs.push_back(MCInstBuilder(RISCV::ADD_UW)
+      MatIntInstrs.push_back(MCInstBuilder(Inst.getOpcode())
                                  .addReg(DestReg)
                                  .addReg(SrcReg)
                                  .addReg(RISCV::X0));
diff --git a/utils/bazel/llvm-project-overlay/llvm/BUILD.bazel b/utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
@@ -2248,7 +2248,6 @@ llvm_target_lib_list = [lib for lib in [
             ("-gen-register-info", "lib/Target/RISCV/RISCVGenRegisterInfo.inc"),
             ("-gen-subtarget", "lib/Target/RISCV/RISCVGenSubtargetInfo.inc"),
             ("-gen-searchable-tables", "lib/Target/RISCV/RISCVGenSearchableTables.inc"),
-	    ("-gen-exegesis", "lib/Target/RISCV/RISCVGenExegesis.inc"),
         ],
         "tbl_deps": [
             ":riscv_isel_target_gen",
