Addressing review comments

Author: AnastasiyaChernikova

llvm/test/tools/llvm-exegesis/RISCV/latency-by-load.s

@@ -42,7 +42,6 @@ LBU-NEXT:     - 'LBU X10 X10 i_0x0'
 
 LUI: LUI: No strategy found to make the execution serial
 
-
 # RUN: llvm-exegesis -mode=latency -mtriple=riscv64-unknown-linux-gnu --mcpu=generic --benchmark-phase=assemble-measured-code -opcode-name=LB | FileCheck --check-prefix=LB %s
 
 LB:      ---

llvm/tools/llvm-exegesis/lib/MCInstrDescView.cpp

@@ -96,11 +96,11 @@ Instruction::Instruction(const MCInstrDesc *Description, StringRef Name,
                          const BitVector *ImplUseRegs,
                          const BitVector *AllDefRegs,
                          const BitVector *AllUseRegs,
-                         const BitVector *NotMemoryRegs)
+                         const BitVector *NonMemoryRegs)
     : Description(*Description), Name(Name), Operands(std::move(Operands)),
       Variables(std::move(Variables)), ImplDefRegs(*ImplDefRegs),
       ImplUseRegs(*ImplUseRegs), AllDefRegs(*AllDefRegs),
-      AllUseRegs(*AllUseRegs), NotMemoryRegs(*NotMemoryRegs) {}
+      AllUseRegs(*AllUseRegs), NonMemoryRegs(*NonMemoryRegs) {}
 
 std::unique_ptr<Instruction>
 Instruction::create(const MCInstrInfo &InstrInfo,
@@ -167,7 +167,7 @@ Instruction::create(const MCInstrInfo &InstrInfo,
   BitVector ImplUseRegs = RATC.emptyRegisters();
   BitVector AllDefRegs = RATC.emptyRegisters();
   BitVector AllUseRegs = RATC.emptyRegisters();
-  BitVector NotMemoryRegs = RATC.emptyRegisters();
+  BitVector NonMemoryRegs = RATC.emptyRegisters();
 
   for (const auto &Op : Operands) {
     if (Op.isReg()) {
@@ -181,7 +181,7 @@ Instruction::create(const MCInstrInfo &InstrInfo,
       if (Op.isUse() && Op.isImplicit())
         ImplUseRegs |= AliasingBits;
       if (Op.isUse() && !Op.isMemory())
-        NotMemoryRegs |= AliasingBits;
+        NonMemoryRegs |= AliasingBits;
     }
   }
   // Can't use make_unique because constructor is private.
@@ -191,7 +191,7 @@ Instruction::create(const MCInstrInfo &InstrInfo,
       BVC.getUnique(std::move(ImplUseRegs)),
       BVC.getUnique(std::move(AllDefRegs)),
       BVC.getUnique(std::move(AllUseRegs)),
-      BVC.getUnique(std::move(NotMemoryRegs))));
+      BVC.getUnique(std::move(NonMemoryRegs))));
 }
 
 const Operand &Instruction::getPrimaryOperand(const Variable &Var) const {
@@ -248,7 +248,7 @@ bool Instruction::hasAliasingRegisters(
 
 bool Instruction::hasAliasingNotMemoryRegisters(
     const BitVector &ForbiddenRegisters) const {
-  return anyCommonExcludingForbidden(AllDefRegs, NotMemoryRegs,
+  return anyCommonExcludingForbidden(AllDefRegs, NonMemoryRegs,
                                      ForbiddenRegisters);
 }
 

llvm/tools/llvm-exegesis/lib/MCInstrDescView.h

@@ -167,14 +167,14 @@ struct Instruction {
   const BitVector &AllDefRegs;  // The set of all aliased def registers.
   const BitVector &AllUseRegs;  // The set of all aliased use registers.
   // The set of all aliased not memory use registers.
-  const BitVector &NotMemoryRegs;
+  const BitVector &NonMemoryRegs;
 
 private:
   Instruction(const MCInstrDesc *Description, StringRef Name,
               SmallVector<Operand, 8> Operands,
               SmallVector<Variable, 4> Variables, const BitVector *ImplDefRegs,
               const BitVector *ImplUseRegs, const BitVector *AllDefRegs,
-              const BitVector *AllUseRegs, const BitVector *NotMemoryRegs);
+              const BitVector *AllUseRegs, const BitVector *NonMemoryRegs);
 };
 
 // Instructions are expensive to instantiate. This class provides a cache of

llvm/tools/llvm-exegesis/lib/PerfHelper.h

@@ -119,7 +119,7 @@ class CounterGroup {
   virtual void start();
 
   /// Stops the measurement of the event.
-  virtual void stop();
+  void stop();
 
   /// Returns the current value of the counter or error if it cannot be read.
   /// FunctionBytes: The benchmark function being executed.