implement sysenter support for system calls

Author: xvanc

src/aero_kernel/src/arch/x86_64/syscall.rs

@@ -10,6 +10,7 @@ use super::interrupts::InterruptErrorStack;
 
 extern "C" {
     fn x86_64_syscall_handler();
+    fn x86_64_sysenter_handler();
 }
 
 const ARCH_SET_GS: usize = 0x1001;
@@ -54,7 +55,7 @@ fn arch_prctl(command: usize, address: usize) -> Result<usize, AeroSyscallError>
 }
 
 #[no_mangle]
-extern "C" fn x86_64_do_syscall(stack: &mut InterruptErrorStack) {
+pub(super) extern "C" fn x86_64_do_syscall(stack: &mut InterruptErrorStack) {
     let stack = &mut stack.stack;
 
     let syscall_number = stack.scratch.rax as usize; // syscall number
@@ -94,8 +95,10 @@ extern "C" fn x86_64_do_syscall(stack: &mut InterruptErrorStack) {
 /// Initializes support for the `syscall` and `sysret` instructions for the
 /// current CPU.
 pub(super) fn init() {
+    let cpuid = CpuId::new();
+
     // Check if syscall is supported as it is a required CPU feature for aero to run.
-    let has_syscall = CpuId::new()
+    let has_syscall = cpuid
         .get_extended_processor_and_feature_identifiers()
         .map_or(false, |i| i.has_syscall_sysret());
 
@@ -107,7 +110,7 @@ pub(super) fn init() {
          * CPU supports them and the target pointer width is 64.
          */
         let syscall_base = GdtEntryType::KERNEL_CODE << 3;
-        let sysret_base = (GdtEntryType::USER_CODE32_UNUSED << 3) | 3;
+        let sysret_base = (GdtEntryType::KERNEL_TLS << 3) | 3;
 
         let star_hi = syscall_base as u32 | ((sysret_base as u32) << 16);
 
@@ -121,4 +124,26 @@ pub(super) fn init() {
         let efer = io::rdmsr(io::IA32_EFER);
         io::wrmsr(io::IA32_EFER, efer | 1);
     }
+
+    /*
+     * Enable support for the `sysenter` instruction for system calls.
+     *
+     * This instruction is only supported on AMD processors in Legacy mode,
+     * not in Long mode (Compatibility or 64-bit modes), so still report support
+     * for it via `cpuid`. In this case the #UD exception is caught to handle the
+     * system call.
+     */
+    let has_sysenter = cpuid
+        .get_feature_info()
+        .map_or(false, |i| i.has_sysenter_sysexit());
+
+    if has_sysenter {
+        unsafe {
+            io::wrmsr(
+                io::IA32_SYSENTER_CS,
+                (GdtEntryType::KERNEL_CODE << 3) as u64,
+            );
+            io::wrmsr(io::IA32_SYSENTER_EIP, x86_64_sysenter_handler as u64);
+        }
+    }
 }

src/aero_kernel/src/arch/x86_64/syscall_handler.asm

@@ -28,6 +28,8 @@ global x86_64_syscall_handler
 %define USERLAND_SS         0x23
 %define USERLAND_CS         0x2b
 
+%define FMASK               0x300  ; TF | DF
+
 ; 64-bit SYSCALL instruction entry point. The instruction supports
 ; to to 6 arguments in registers.
 ;
@@ -92,3 +94,66 @@ x86_64_syscall_handler:
 
     swapgs
     o64 sysret
+
+; 64-bit SYSENTER entry point
+;
+; The SYSENTER mechanism performs a fast transition to the kernel.
+; The new CS is loaded from the IA32_SYSENTER_CS MSR, and the new instruction
+; and stack pointers are loaded from IA32_SYSENTER_EIP and IA32_SYSENTER_ESP,
+; respectively. RFLAGS.IF is cleared, but other flags are unchanged.
+;
+; As the instruction does not save *any* state, the user is required to provide
+; the return RIP and RSP in the RCX and R11 registers, respectively. These
+; addresses must be canonical.
+;
+; The instruction expects the call number and arguments in the same registers as
+; for SYSCALL.
+;
+section .text.x86_64_sysenter_handler
+global  x86_64_sysenter_handler:function (x86_64_sysenter_handler.end - x86_64_sysenter_handler)
+align   16
+x86_64_sysenter_handler:
+    swapgs
+
+    ; Build the interrupt frame expected by the kernel.
+    push    USERLAND_SS
+    push    r11
+    pushfq
+    push    USERLAND_CS
+    push    rcx
+
+    ; Mask the same flags as for SYSCALL.
+    ; Note that up to this pont the code can be single-stepped if the user sets TF.
+    pushfq
+    and     dword [rsp], 0x300
+    popfq
+
+    push    rax
+    push_scratch
+    push_preserved
+    push    0
+
+    ; Sore the stack pointer (interrupt frame pointer) in RBP for save keeping,
+    ; and align the stack as specified by the SysV calling convention.
+    mov     rbp, rsp
+    and     rsp, ~0xf
+
+    mov     rdi, rbp
+    call    x86_64_do_syscall
+
+    ; Reload the stack pointer, skipping the error code.
+    lea     rsp, [rbp + 8]
+    pop_preserved
+    pop_scratch
+
+    ; Restore RFLAGS
+    add     rsp, 16
+    popfq
+
+    ; Move the return RIP and RSP into the registers expected by SYSEXIT.
+    mov     rdx, rcx
+    mov     rcx, r11
+
+    swapgs
+    o64 sysexit
+.end:

src/aero_kernel/src/arch/x86_64/task.rs

@@ -375,7 +375,11 @@ pub fn arch_task_spinup(from: &mut ArchTask, to: &ArchTask) {
     }
 
     unsafe {
-        super::gdt::get_task_state_segement().rsp[0] = to.context_switch_rsp.as_u64();
+        // Load the new thread's kernel stack pointer everywhere it's needed.
+        let kstackp = to.context_switch_rsp.as_u64();
+        super::gdt::get_task_state_segement().rsp[0] = kstackp;
+        io::wrmsr(io::IA32_SYSENTER_ESP, kstackp);
+
         task_spinup(&mut from.context, to.context.as_ref());
 
         // make a restore point for the current FS base.

src/aero_kernel/src/utils/io.rs

@@ -39,6 +39,10 @@ pub const IA32_LSTAR: u32 = 0xc0000082;
 /// System Call Flag Mask (R/W).
 pub const IA32_FMASK: u32 = 0xc0000084;
 
+pub const IA32_SYSENTER_CS: u32 = 0x174;
+pub const IA32_SYSENTER_ESP: u32 = 0x175;
+pub const IA32_SYSENTER_EIP: u32 = 0x176;
+
 /// APIC Location and Status (R/W).
 ///
 /// ```text