Question regarding NexSys_Video example

[ztachip]

I am trying the NexSys_Video_example
In file nexsysvideo_ddr3.v, you set
.DQ_BITS(8), //width of DQ
.BYTE_LANES(1), //number of DDR3 modules to be controlled

Does this mean NexSys has just a 8-bit DDR bus? This seems very slow for this board since Diligent provides 16-bit DDR on other boards normally.
I tried to find the schematics for NexSys_Video board but seems Diligent did not provide it.

Thanks

[ztachip]

In the top component, you have 1 bit for ddr3_dqs but 2 bit for ddr3_dm
Should they be the same? Since they both reference byte lane?

[AngeloJacobo]

Hi @ztachip, looking on this reference manual, you are right nexys video is 16 bit wide for DDR3:
https://digilent.com/reference/programmable-logic/nexys-video/reference-manual

The example demo only stores 8 bits from UART, so BYTE_LANES of 1 is enough. But if you would like to use this at full capacity (16-bit DDR), change this to:

.DQ_BITS(8), //width of DQ
.BYTE_LANES(2), //number of bytes lanes, 2 byte-lanes for x16

(note: only BYTE_LANES will be changed, DQ_BITS is still 8)

If the full 16-bit will be used, then ddr3_dqs and ddr3_dm must both be 2-bits. On the xdc file, please also uncomment the dqs for bit [1]:
https://github.com/AngeloJacobo/UberDDR3/blob/main/example_demo/nexys_video/Nexys-video.xdc#L221-L229

[ztachip]

I tried to port your reference design to Diligent A7
https://digilent.com/reference/programmable-logic/arty-a7/reference-manual?
Below is the XDC for the board

set_property SLEW FAST [get_ports {ddr3_dq[0]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[0]}]
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[0]}]
set_property PACKAGE_PIN K5 [get_ports {ddr3_dq[0]}]

set_property SLEW FAST [get_ports {ddr3_dq[1]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[1]}]
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[1]}]
set_property PACKAGE_PIN L3 [get_ports {ddr3_dq[1]}]

set_property SLEW FAST [get_ports {ddr3_dq[2]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[2]}]
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[2]}]
set_property PACKAGE_PIN K3 [get_ports {ddr3_dq[2]}]

set_property SLEW FAST [get_ports {ddr3_dq[3]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[3]}]
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[3]}]
set_property PACKAGE_PIN L6 [get_ports {ddr3_dq[3]}]

set_property SLEW FAST [get_ports {ddr3_dq[4]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[4]}]
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[4]}]
set_property PACKAGE_PIN M3 [get_ports {ddr3_dq[4]}]

set_property SLEW FAST [get_ports {ddr3_dq[5]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[5]}]
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[5]}]
set_property PACKAGE_PIN M1 [get_ports {ddr3_dq[5]}]

set_property SLEW FAST [get_ports {ddr3_dq[6]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[6]}]
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[6]}]
set_property PACKAGE_PIN L4 [get_ports {ddr3_dq[6]}]

set_property SLEW FAST [get_ports {ddr3_dq[7]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[7]}]
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[7]}]
set_property PACKAGE_PIN M2 [get_ports {ddr3_dq[7]}]

set_property SLEW FAST [get_ports {ddr3_dq[8]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[8]}]
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[8]}]
set_property PACKAGE_PIN V4 [get_ports {ddr3_dq[8]}]

set_property SLEW FAST [get_ports {ddr3_dq[9]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[9]}]
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[9]}]
set_property PACKAGE_PIN T5 [get_ports {ddr3_dq[9]}]

set_property SLEW FAST [get_ports {ddr3_dq[10]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[10]}]
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[10]}]
set_property PACKAGE_PIN U4 [get_ports {ddr3_dq[10]}]

set_property SLEW FAST [get_ports {ddr3_dq[11]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[11]}]
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[11]}]
set_property PACKAGE_PIN V5 [get_ports {ddr3_dq[11]}]

set_property SLEW FAST [get_ports {ddr3_dq[12]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[12]}]
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[12]}]
set_property PACKAGE_PIN V1 [get_ports {ddr3_dq[12]}]

set_property SLEW FAST [get_ports {ddr3_dq[13]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[13]}]
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[13]}]
set_property PACKAGE_PIN T3 [get_ports {ddr3_dq[13]}]

set_property SLEW FAST [get_ports {ddr3_dq[14]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[14]}]
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[14]}]
set_property PACKAGE_PIN U3 [get_ports {ddr3_dq[14]}]

set_property SLEW FAST [get_ports {ddr3_dq[15]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[15]}]
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[15]}]
set_property PACKAGE_PIN R3 [get_ports {ddr3_dq[15]}]

set_property SLEW FAST [get_ports {ddr3_addr[13]}]
set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[13]}]
set_property PACKAGE_PIN T8 [get_ports {ddr3_addr[13]}]

set_property SLEW FAST [get_ports {ddr3_addr[12]}]
set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[12]}]
set_property PACKAGE_PIN T6 [get_ports {ddr3_addr[12]}]

set_property SLEW FAST [get_ports {ddr3_addr[11]}]
set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[11]}]
set_property PACKAGE_PIN U6 [get_ports {ddr3_addr[11]}]

set_property SLEW FAST [get_ports {ddr3_addr[10]}]
set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[10]}]
set_property PACKAGE_PIN R6 [get_ports {ddr3_addr[10]}]

set_property SLEW FAST [get_ports {ddr3_addr[9]}]
set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[9]}]
set_property PACKAGE_PIN V7 [get_ports {ddr3_addr[9]}]

set_property SLEW FAST [get_ports {ddr3_addr[8]}]
set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[8]}]
set_property PACKAGE_PIN R8 [get_ports {ddr3_addr[8]}]

set_property SLEW FAST [get_ports {ddr3_addr[7]}]
set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[7]}]
set_property PACKAGE_PIN U7 [get_ports {ddr3_addr[7]}]

set_property SLEW FAST [get_ports {ddr3_addr[6]}]
set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[6]}]
set_property PACKAGE_PIN V6 [get_ports {ddr3_addr[6]}]

set_property SLEW FAST [get_ports {ddr3_addr[5]}]
set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[5]}]
set_property PACKAGE_PIN R7 [get_ports {ddr3_addr[5]}]

set_property SLEW FAST [get_ports {ddr3_addr[4]}]
set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[4]}]
set_property PACKAGE_PIN N6 [get_ports {ddr3_addr[4]}]

set_property SLEW FAST [get_ports {ddr3_addr[3]}]
set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[3]}]
set_property PACKAGE_PIN T1 [get_ports {ddr3_addr[3]}]

set_property SLEW FAST [get_ports {ddr3_addr[2]}]
set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[2]}]
set_property PACKAGE_PIN N4 [get_ports {ddr3_addr[2]}]

set_property SLEW FAST [get_ports {ddr3_addr[1]}]
set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[1]}]
set_property PACKAGE_PIN M6 [get_ports {ddr3_addr[1]}]

set_property SLEW FAST [get_ports {ddr3_addr[0]}]
set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[0]}]
set_property PACKAGE_PIN R2 [get_ports {ddr3_addr[0]}]

set_property SLEW FAST [get_ports {ddr3_ba[2]}]
set_property IOSTANDARD SSTL135 [get_ports {ddr3_ba[2]}]
set_property PACKAGE_PIN P2 [get_ports {ddr3_ba[2]}]

set_property SLEW FAST [get_ports {ddr3_ba[1]}]
set_property IOSTANDARD SSTL135 [get_ports {ddr3_ba[1]}]
set_property PACKAGE_PIN P4 [get_ports {ddr3_ba[1]}]

set_property SLEW FAST [get_ports {ddr3_ba[0]}]
set_property IOSTANDARD SSTL135 [get_ports {ddr3_ba[0]}]
set_property PACKAGE_PIN R1 [get_ports {ddr3_ba[0]}]

set_property SLEW FAST [get_ports ddr3_ras_n]
set_property IOSTANDARD SSTL135 [get_ports ddr3_ras_n]
set_property PACKAGE_PIN P3 [get_ports ddr3_ras_n]

set_property SLEW FAST [get_ports ddr3_cas_n]
set_property IOSTANDARD SSTL135 [get_ports ddr3_cas_n]
set_property PACKAGE_PIN M4 [get_ports ddr3_cas_n]

set_property SLEW FAST [get_ports ddr3_we_n]
set_property IOSTANDARD SSTL135 [get_ports ddr3_we_n]
set_property PACKAGE_PIN P5 [get_ports ddr3_we_n]

set_property SLEW FAST [get_ports ddr3_reset_n]
set_property IOSTANDARD SSTL135 [get_ports ddr3_reset_n]
set_property PACKAGE_PIN K6 [get_ports ddr3_reset_n]

set_property SLEW FAST [get_ports ddr3_cke]
set_property IOSTANDARD SSTL135 [get_ports ddr3_cke]
set_property PACKAGE_PIN N5 [get_ports ddr3_cke]

set_property SLEW FAST [get_ports ddr3_odt]
set_property IOSTANDARD SSTL135 [get_ports ddr3_odt]
set_property PACKAGE_PIN R5 [get_ports ddr3_odt]

set_property SLEW FAST [get_ports ddr3_cs_n]
set_property IOSTANDARD LVCMOS33 [get_ports ddr3_cs_n]
set_property PACKAGE_PIN U8 [get_ports ddr3_cs_n]

set_property SLEW FAST [get_ports {ddr3_dm[0]}]
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dm[0]}]
set_property PACKAGE_PIN L1 [get_ports {ddr3_dm[0]}]

set_property SLEW FAST [get_ports {ddr3_dm[1]}]
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dm[1]}]
set_property PACKAGE_PIN U1 [get_ports {ddr3_dm[1]}]

set_property SLEW FAST [get_ports {ddr3_dqs_p[0]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dqs_p[0]}]
set_property IOSTANDARD DIFF_SSTL135 [get_ports {ddr3_dqs_p[0]}]

set_property SLEW FAST [get_ports {ddr3_dqs_n[0]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dqs_n[0]}]
set_property IOSTANDARD DIFF_SSTL135 [get_ports {ddr3_dqs_n[0]}]
set_property PACKAGE_PIN N2 [get_ports {ddr3_dqs_p[0]}]
set_property PACKAGE_PIN N1 [get_ports {ddr3_dqs_n[0]}]

set_property SLEW FAST [get_ports {ddr3_dqs_p[1]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dqs_p[1]}]
set_property IOSTANDARD DIFF_SSTL135 [get_ports {ddr3_dqs_p[1]}]

set_property SLEW FAST [get_ports {ddr3_dqs_n[1]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dqs_n[1]}]
set_property IOSTANDARD DIFF_SSTL135 [get_ports {ddr3_dqs_n[1]}]
set_property PACKAGE_PIN U2 [get_ports {ddr3_dqs_p[1]}]
set_property PACKAGE_PIN V2 [get_ports {ddr3_dqs_n[1]}]

set_property SLEW FAST [get_ports ddr3_clk_p]
set_property IOSTANDARD DIFF_SSTL135 [get_ports ddr3_clk_p]

set_property SLEW FAST [get_ports ddr3_clk_n]
set_property IOSTANDARD DIFF_SSTL135 [get_ports ddr3_clk_n]
set_property PACKAGE_PIN U9 [get_ports ddr3_clk_p]
set_property PACKAGE_PIN V9 [get_ports ddr3_clk_n]

[ztachip]

But I have error
[DRC BIVC-1] Bank IO standard Vcc: Conflicting Vcc voltages in bank 34. For example, the following two ports in this bank have conflicting VCCOs:
ddr3_clk_p (DIFF_SSTL135, requiring VCCO=1.350) and ddr3_cs_n (LVCMOS33, requiring VCCO=3.300)
[DRC BIVRU-1] Bank IO standard Vref utilization: Bank 34 contains ports that use a reference voltage. In order to use such standards in a bank that is not configured to use INTERNAL_VREF, the bank's VREF pin must be used to supply the appropriate voltage. Example port: ddr3_dq[0] (SSTL135). However, the following VREF sites are occupied and can't be used to supply the necessary voltage:
site IOB_X1Y61 (occupied by port ddr3_odt).
Free up VREF sites or create an appropriate INTERNAL_VREF constraint.

[ztachip]

I think I am still missing something on the XDC? Can you help?
Thanks

[AngeloJacobo]

Hi @ztachip , based on the error:
Free up VREF sites or create an appropriate INTERNAL_VREF constraint.

Maybe the internal VREF constraint is missing on the constraint file, I tried to generate MIG for Arty A7 and here is the constraint for internal VREF:
set_property INTERNAL_VREF 0.675 [get_iobanks 34]

The constraints used by MIG will usually work for UberDDR3 so this internal VREF might fix the error.

[ztachip]

Thanks. This fix the VREF error
But I have VCCO error and it gives different conflicting voltage requirements between 2 pins. How should I resolve this?

[DRC BIVC-1] Bank IO standard Vcc: Conflicting Vcc voltages in bank 34. For example, the following two ports in this bank have conflicting VCCOs:
ddr3_clk_p (DIFF_SSTL135, requiring VCCO=1.350) and ddr3_cs_n (LVCMOS33, requiring VCCO=3.300)

Thanks

[AngeloJacobo]

Nice to hear that. Looking on the constraint output of MIG for cs_n:

set_property SLEW FAST [get_ports {ddr3_cs_n[0]}]
set_property IOSTANDARD SSTL135 [get_ports {ddr3_cs_n[0]}]
set_property PACKAGE_PIN U8 [get_ports {ddr3_cs_n[0]}]

Switching to SSTL135 might fix the issue.

[ztachip]

I managed to build correctly for the Arty-A7
But the issue is the o_wb_stall stays high

Is the way I instantiate DDR3 controller on Arty-A7 correct?

I configure DDR3 controller has followed:
ddr3_top #(
.CONTROLLER_CLK_PERIOD(12_000), //12_000ps, clock period of the controller interface
.DDR3_CLK_PERIOD(3_000), //3_000ps, clock period of the DDR3 RAM device (must be 1/4 of the CONTROLLER_CLK_PERIOD)
.ROW_BITS(14), //width of row address
.COL_BITS(10), //width of column address
.BA_BITS(3), //width of bank address
.DQ_BITS(8), //width of DQ
.BYTE_LANES(2), //number of DDR3 modules to be controlled
.AUX_WIDTH(4), //width of aux line (must be >= 4)
.WB2_ADDR_BITS(32), //width of 2nd wishbone address bus
.WB2_DATA_BITS(32), //width of 2nd wishbone data bus
.MICRON_SIM(0), //enable faster simulation for micron ddr3 model (shorten POWER_ON_RESET_HIGH and INITIAL_CKE_LOW)
.ODELAY_SUPPORTED(0), //set to 1 when ODELAYE2 is supported
.SECOND_WISHBONE(0) //set to 1 if 2nd wishbone is needed
) ddr3_top_inst

Thanks

[AngeloJacobo]

Hi @ztachip , yes this should be correct. I'm sorry, it seems this is a problem on my controller, I forgot to turn off ECC_TEST which I used to test the newest feature which is ECC. The current commit should now work.

[ztachip]

o_wb_stall still stays high. May be there is something wrong with my pin assignments.
Are there any signals you like to capture?
I attached here the XDC (main.xdc and ddr3.xdc) and top component (nexysvideo_ddr3.v) of the test.
main.xdc and ddr3.xdc are the only 2 constrains that I have, is this correct? You have any other constrains for DDR controller?
I rename files to *.txt since github does no accept attachment of unknown file type.

ddr3.txt
main.txt
nexysvideo_ddr3.txt

[ztachip]

I have trouble to use the clock_wizard that comes with your example.
So I create it instead using Vivado GUI.
Attached is the description of the clocks that I created

[ztachip]

Is the board below the one you use for your test? Since I see references to this board in your folder.
https://digilent.com/reference/programmable-logic/nexys-video/start
I am thinking to upgrade the XIlinx board since my board (Arty-A7) is running out of steam
This probably easier if we referencing the same hardware.

[regymm]

Hi, I was using Nexys Video for testing UberDDR3. For the example files here, only 8-bit is used, because somehow now OpenXC7, the open-source(non-Vivado) toolchains complains for 16-bit. Vivado will be fine with both 8 and 16 bits.

For the constraint file, Nexys-video-vivado.xdc is required for Vivado. Please try using Makefile.vivado to compile, this should give you a working bitstream.

(In some cases, if the Makefile.vivado gives error, you may need to change this section of makefile:)

${BUILDDIR}:
	mkdir -m 777 -p ${BUILDDIR}

[AngeloJacobo]

Hi @ztachip , @regymm is the one with the Nexys Video, he was the one who was able to make UberDDR3 work on that board.

I also don't have Nexys Video board on me. The Xilinx FPGA boards I have here are:

• Enclustra KX2-ST1
• ALINX AX7325B
• ALINX AX7103
• QMTech Wukong board
• Arty S7-50

I don't know if any of these boards satisfy the requirements for ztachip.