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[llvm] Add support for llvm IR atomicrmw fminimum/fmaximum instructions (llvm#136759)
This patch adds support for LLVM IR atomicrmw `fmaximum` and `fminimum` instructions. These mirror the `llvm.maximum.*` and `llvm.minimum.*` instructions, but are atomic and use IEEE754 2019 handling for NaNs, which is different to `fmax` and `fmin`. See: https://llvm.org/docs/LangRef.html#llvm-minimum-intrinsic for more details. Future changes will allow this LLVM IR to be lowered to specialised assembler instructions on suitable targets, such as AArch64.
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‎llvm/docs/GlobalISel/GenericOpcode.rst

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@@ -922,7 +922,8 @@ operands.
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G_ATOMICRMW_MIN, G_ATOMICRMW_UMAX,
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G_ATOMICRMW_UMIN, G_ATOMICRMW_FADD,
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G_ATOMICRMW_FSUB, G_ATOMICRMW_FMAX,
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G_ATOMICRMW_FMIN, G_ATOMICRMW_UINC_WRAP,
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G_ATOMICRMW_FMIN, G_ATOMICRMW_FMAXIMUM,
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G_ATOMICRMW_FMINIMUM, G_ATOMICRMW_UINC_WRAP,
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G_ATOMICRMW_UDEC_WRAP, G_ATOMICRMW_USUB_COND,
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G_ATOMICRMW_USUB_SAT
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‎llvm/docs/LangRef.rst

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@@ -11598,6 +11598,8 @@ operation. The operation must be one of the following keywords:
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- fsub
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- fmax
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- fmin
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- fmaximum
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- fminimum
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- uinc_wrap
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- udec_wrap
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- usub_cond
@@ -11607,7 +11609,7 @@ For most of these operations, the type of '<value>' must be an integer
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type whose bit width is a power of two greater than or equal to eight
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and less than or equal to a target-specific size limit. For xchg, this
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may also be a floating point or a pointer type with the same size constraints
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as integers. For fadd/fsub/fmax/fmin, this must be a floating-point
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as integers. For fadd/fsub/fmax/fmin/fmaximum/fminimum, this must be a floating-point
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or fixed vector of floating-point type. The type of the '``<pointer>``'
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operand must be a pointer to that type. If the ``atomicrmw`` is marked
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as ``volatile``, then the optimizer is not allowed to modify the
@@ -11648,8 +11650,10 @@ operation argument:
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- umin: ``*ptr = *ptr < val ? *ptr : val`` (using an unsigned comparison)
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- fadd: ``*ptr = *ptr + val`` (using floating point arithmetic)
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- fsub: ``*ptr = *ptr - val`` (using floating point arithmetic)
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- fmax: ``*ptr = maxnum(*ptr, val)`` (match the `llvm.maxnum.*`` intrinsic)
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- fmin: ``*ptr = minnum(*ptr, val)`` (match the `llvm.minnum.*`` intrinsic)
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- fmax: ``*ptr = maxnum(*ptr, val)`` (match the `llvm.maxnum.*` intrinsic)
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- fmin: ``*ptr = minnum(*ptr, val)`` (match the `llvm.minnum.*` intrinsic)
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- fmaximum: ``*ptr = maximum(*ptr, val)`` (match the `llvm.maximum.*` intrinsic)
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- fminimum: ``*ptr = minimum(*ptr, val)`` (match the `llvm.minimum.*` intrinsic)
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- uinc_wrap: ``*ptr = (*ptr u>= val) ? 0 : (*ptr + 1)`` (increment value with wraparound to zero when incremented above input value)
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- udec_wrap: ``*ptr = ((*ptr == 0) || (*ptr u> val)) ? val : (*ptr - 1)`` (decrement with wraparound to input value when decremented below zero).
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- usub_cond: ``*ptr = (*ptr u>= val) ? *ptr - val : *ptr`` (subtract only if no unsigned overflow).

‎llvm/docs/ReleaseNotes.md

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@@ -72,6 +72,9 @@ Changes to LLVM infrastructure
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themselves (i.e., the `TargetIntrinsicInfo` class).
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* Fix Microsoft demangling of string literals to be stricter
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(#GH129970))
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* Added the support for ``fmaximum`` and ``fminimum`` in ``atomicrmw`` instruction. The
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comparison is expected to match the behavior of ``llvm.maximum.*`` and
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``llvm.minimum.*`` respectively.
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Changes to building LLVM
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------------------------

‎llvm/include/llvm-c/Core.h

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@@ -393,6 +393,12 @@ typedef enum {
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LLVMAtomicRMWBinOpUSubCond, /**<Subtracts the value only if no unsigned
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overflow */
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LLVMAtomicRMWBinOpUSubSat, /**<Subtracts the value, clamping to zero */
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LLVMAtomicRMWBinOpFMaximum, /**< Sets the value if it's greater than the
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original using an floating point comparison and
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return the old one */
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LLVMAtomicRMWBinOpFMinimum, /**< Sets the value if it's smaller than the
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original using an floating point comparison and
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return the old one */
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} LLVMAtomicRMWBinOp;
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typedef enum {

‎llvm/include/llvm/AsmParser/LLToken.h

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@@ -276,6 +276,8 @@ enum Kind {
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kw_umin,
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kw_fmax,
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kw_fmin,
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kw_fmaximum,
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kw_fminimum,
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kw_uinc_wrap,
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kw_udec_wrap,
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kw_usub_cond,

‎llvm/include/llvm/Bitcode/LLVMBitCodes.h

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@@ -504,7 +504,9 @@ enum RMWOperations {
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RMW_UINC_WRAP = 15,
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RMW_UDEC_WRAP = 16,
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RMW_USUB_COND = 17,
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RMW_USUB_SAT = 18
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RMW_USUB_SAT = 18,
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RMW_FMAXIMUM = 19,
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RMW_FMINIMUM = 20,
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};
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/// OverflowingBinaryOperatorOptionalFlags - Flags for serializing

‎llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h

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@@ -1663,6 +1663,42 @@ class MachineIRBuilder {
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const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val,
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MachineMemOperand &MMO);
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/// Build and insert `OldValRes<def> = G_ATOMICRMW_FMAXIMUM Addr, Val, MMO`.
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///
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/// Atomically replace the value at \p Addr with the floating point maximum of
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/// \p Val and the original value. Puts the original value from \p Addr in \p
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/// OldValRes.
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///
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/// \pre setBasicBlock or setMI must have been called.
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/// \pre \p OldValRes must be a generic virtual register.
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/// \pre \p Addr must be a generic virtual register with pointer type.
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/// \pre \p OldValRes, and \p Val must be generic virtual registers of the
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/// same type.
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///
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/// \return a MachineInstrBuilder for the newly created instruction.
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MachineInstrBuilder buildAtomicRMWFMaximum(const DstOp &OldValRes,
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const SrcOp &Addr,
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const SrcOp &Val,
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MachineMemOperand &MMO);
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/// Build and insert `OldValRes<def> = G_ATOMICRMW_FMINIMUM Addr, Val, MMO`.
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///
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/// Atomically replace the value at \p Addr with the floating point minimum of
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/// \p Val and the original value. Puts the original value from \p Addr in \p
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/// OldValRes.
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///
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/// \pre setBasicBlock or setMI must have been called.
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/// \pre \p OldValRes must be a generic virtual register.
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/// \pre \p Addr must be a generic virtual register with pointer type.
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/// \pre \p OldValRes, and \p Val must be generic virtual registers of the
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/// same type.
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///
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/// \return a MachineInstrBuilder for the newly created instruction.
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MachineInstrBuilder buildAtomicRMWFMinimum(const DstOp &OldValRes,
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const SrcOp &Addr,
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const SrcOp &Val,
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MachineMemOperand &MMO);
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/// Build and insert `OldValRes<def> = G_ATOMICRMW_USUB_COND Addr, Val, MMO`.
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///
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/// Atomically replace the value at \p Addr with the original value minus \p

‎llvm/include/llvm/CodeGen/ISDOpcodes.h

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@@ -1376,6 +1376,8 @@ enum NodeType {
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ATOMIC_LOAD_FSUB,
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ATOMIC_LOAD_FMAX,
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ATOMIC_LOAD_FMIN,
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ATOMIC_LOAD_FMAXIMUM,
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ATOMIC_LOAD_FMINIMUM,
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ATOMIC_LOAD_UINC_WRAP,
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ATOMIC_LOAD_UDEC_WRAP,
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ATOMIC_LOAD_USUB_COND,

‎llvm/include/llvm/CodeGen/SelectionDAGNodes.h

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@@ -1517,6 +1517,8 @@ class MemSDNode : public SDNode {
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case ISD::ATOMIC_LOAD_FSUB:
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case ISD::ATOMIC_LOAD_FMAX:
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case ISD::ATOMIC_LOAD_FMIN:
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case ISD::ATOMIC_LOAD_FMAXIMUM:
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case ISD::ATOMIC_LOAD_FMINIMUM:
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case ISD::ATOMIC_LOAD_UINC_WRAP:
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case ISD::ATOMIC_LOAD_UDEC_WRAP:
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case ISD::ATOMIC_LOAD_USUB_COND:
@@ -1603,6 +1605,8 @@ class AtomicSDNode : public MemSDNode {
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N->getOpcode() == ISD::ATOMIC_LOAD_FSUB ||
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N->getOpcode() == ISD::ATOMIC_LOAD_FMAX ||
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N->getOpcode() == ISD::ATOMIC_LOAD_FMIN ||
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N->getOpcode() == ISD::ATOMIC_LOAD_FMAXIMUM ||
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N->getOpcode() == ISD::ATOMIC_LOAD_FMINIMUM ||
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N->getOpcode() == ISD::ATOMIC_LOAD_UINC_WRAP ||
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N->getOpcode() == ISD::ATOMIC_LOAD_UDEC_WRAP ||
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N->getOpcode() == ISD::ATOMIC_LOAD_USUB_COND ||

‎llvm/include/llvm/IR/Instructions.h

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@@ -751,6 +751,14 @@ class AtomicRMWInst : public Instruction {
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/// \p minnum matches the behavior of \p llvm.minnum.*.
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FMin,
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/// *p = maximum(old, v)
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/// \p maximum matches the behavior of \p llvm.maximum.*.
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FMaximum,
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/// *p = minimum(old, v)
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/// \p minimum matches the behavior of \p llvm.minimum.*.
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FMinimum,
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/// Increment one up to a maximum value.
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/// *p = (old u>= v) ? 0 : (old + 1)
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UIncWrap,
@@ -812,6 +820,8 @@ class AtomicRMWInst : public Instruction {
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case AtomicRMWInst::FSub:
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case AtomicRMWInst::FMax:
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case AtomicRMWInst::FMin:
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case AtomicRMWInst::FMaximum:
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case AtomicRMWInst::FMinimum:
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return true;
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default:
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return false;

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