Merge pull request chipsalliance#512 from antmicro/kr/change_remove_message

systemverilog-plugin: update remove module message

Author: kamilrakoczy

systemverilog-plugin/UhdmAst.cc

@@ -2015,7 +2015,7 @@ void UhdmAst::process_design()
                 current_node->children.push_back(pair.second);
             }
         } else {
-            log_warning("Removing unused module: %s from the design.\n", pair.second->str.c_str());
+            log_warning("Removing unelaborated module: %s from the design.\n", pair.second->str.c_str());
             // TODO: This should be properly erased from the module, but it seems that it's
             // needed to resolve scope
             delete pair.second;