Build(deps): Bump yosys-f4pga-plugins from 56f957c to 8edc027 (chipsalliance#1762)

Bumps
[yosys-f4pga-plugins](https://github.com/chipsalliance/yosys-f4pga-plugins)
from `56f957c` to `8edc027`.
<details>
<summary>Commits</summary>
<ul>
<li><a
href="https://github.com/chipsalliance/yosys-f4pga-plugins/commit/8edc027cdc484f86c5ac8698c696c74d04e6f92e"><code>8edc027</code></a>
Merge pull request <a
href="https://redirect.github.com/chipsalliance/yosys-f4pga-plugins/issues/523">#523</a>
from antmicro/kr/fix_anonymous_enum</li>
<li><a
href="https://github.com/chipsalliance/yosys-f4pga-plugins/commit/cb6c85575bda3d06d6e798d11010957d39391ce1"><code>cb6c855</code></a>
systemverilog-plugin: fix anonymous enum when declared in
submodules</li>
<li><a
href="https://github.com/chipsalliance/yosys-f4pga-plugins/commit/4ace42c7389a37251ee3f7227772e22a797bed36"><code>4ace42c</code></a>
systemverilog-plugin: add MAKE_INTERNAL_ID macro</li>
<li>See full diff in <a
href="https://github.com/chipsalliance/yosys-f4pga-plugins/compare/56f957caa573658015cc4256cd9ebf2a0cc70a19...8edc027cdc484f86c5ac8698c696c74d04e6f92e">compare
view</a></li>
</ul>
</details>
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</details>

Author: kamilrakoczy

formal/passlist.txt

@@ -475,6 +475,7 @@ yosys:arch/gowin/compare.v
 yosys:arch/ice40/rom.v
 yosys:arch/xilinx/bug3670.v
 yosys:arch/xilinx/mul_unsigned.v
+yosys:asicworld/code_hdl_models_cam.v
 yosys:asicworld/code_hdl_models_clk_div.v
 yosys:asicworld/code_hdl_models_decoder_2to4_gates.v
 yosys:asicworld/code_hdl_models_decoder_using_assign.v
@@ -488,7 +489,6 @@ yosys:asicworld/code_hdl_models_encoder_using_case.v
 yosys:asicworld/code_hdl_models_encoder_using_if.v
 yosys:asicworld/code_hdl_models_full_adder_gates.v
 yosys:asicworld/code_hdl_models_full_subtracter_gates.v
-yosys:asicworld/code_hdl_models_GrayCounter.v
 yosys:asicworld/code_hdl_models_gray_counter.v
 yosys:asicworld/code_hdl_models_half_adder_gates.v
 yosys:asicworld/code_hdl_models_lfsr.v
@@ -532,7 +532,6 @@ yosys:asicworld/code_verilog_tutorial_escape_id.v
 yosys:asicworld/code_verilog_tutorial_explicit.v
 yosys:asicworld/code_verilog_tutorial_first_counter.v
 yosys:asicworld/code_verilog_tutorial_flip_flop.v
-yosys:asicworld/code_verilog_tutorial_fsm_full.v
 yosys:asicworld/code_verilog_tutorial_if_else.v
 yosys:asicworld/code_verilog_tutorial_multiply.v
 yosys:asicworld/code_verilog_tutorial_mux_21.v
@@ -602,7 +601,6 @@ yosys:sim/sdffe.v
 yosys:simple/aes_kexp128.v
 yosys:simple/always01.v
 yosys:simple/always02.v
-yosys:simple/always03.v
 yosys:simple/arraycells.v
 yosys:simple/arrays01.v
 yosys:simple/arrays02.sv
@@ -654,14 +652,12 @@ yosys:simple/module_scope_case.v
 yosys:simple/named_genblk.v
 yosys:simple/nested_genblk_resolve.v
 yosys:simple/omsp_dbg_uart.v
-yosys:simple/operators.v
 yosys:simple/param_attr.v
 yosys:simple/repwhile.v
 yosys:simple/retime.v
 yosys:simple/rotate.v
 yosys:simple/scopes.v
 yosys:simple/signedexpr.v
-yosys:simple/sincos.v
 yosys:simple/specify.v
 yosys:simple/string_format.v
 yosys:simple/subbytes.v

formal/skiplist.txt

@@ -55,6 +55,11 @@
 # wires to cells and the fact, that currently formal verification
 # requires the same order of assignments
 yosys:opt/opt_lut.v
+yosys:simple/always03.v
+yosys:simple/operators.v
+yosys:asicworld/code_verilog_tutorial_fsm_full.v
+yosys:asicworld/code_hdl_models_GrayCounter.v
+yosys:simple/sincos.v
 ########################################################################################
 # Type parameters in top modules cause the modules to be renamed
 # and handled incorrectly in verification scripts.