Added device support for the SSE-320-FVP

Author: Evagan2018

RTE/_Debug_CS320/RTE_Components.h

@@ -0,0 +1,42 @@
+/*
+ * CSOLUTION generated file: DO NOT EDIT!
+ * Generated by: csolution version 2.7.0
+ *
+ * Project: 'Hello.Debug+CS320' 
+ * Target:  'Debug+CS320' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File: 
+ */
+#define CMSIS_device_header "SSE320.h"
+
+/* ARM::CMSIS Driver:[email protected] */
+#define RTE_USART0      1
+
+/* ARM::CMSIS-Compiler:STDERR:[email protected] */
+#define RTE_CMSIS_Compiler_STDERR                /* CMSIS-Compiler STDERR */
+#define RTE_CMSIS_Compiler_STDERR_Custom         /* CMSIS-Compiler STDERR: Custom */
+/* ARM::CMSIS-Compiler:STDIN:[email protected] */
+#define RTE_CMSIS_Compiler_STDIN                 /* CMSIS-Compiler STDIN */
+#define RTE_CMSIS_Compiler_STDIN_Custom          /* CMSIS-Compiler STDIN: Custom */
+/* ARM::CMSIS-Compiler:STDOUT:[email protected] */
+#define RTE_CMSIS_Compiler_STDOUT                /* CMSIS-Compiler STDOUT */
+#define RTE_CMSIS_Compiler_STDOUT_Custom         /* CMSIS-Compiler STDOUT: Custom */
+/* ARM::CMSIS:RTOS2:Keil RTX5&[email protected] */
+#define RTE_CMSIS_RTOS2                 /* CMSIS-RTOS2 */
+#define RTE_CMSIS_RTOS2_RTX5            /* CMSIS-RTOS2 Keil RTX5 */
+#define RTE_CMSIS_RTOS2_RTX5_SOURCE     /* CMSIS-RTOS2 Keil RTX5 Source */
+/* ARM::Device:Native Driver:[email protected] */
+#define RTE_MPS3_IO      1
+/* ARM::Device:Native Driver:[email protected] */
+#define RTE_SYSCOUNTER      1
+/* ARM::Device:Native Driver:[email protected] */
+#define RTE_TIMEOUT      1
+
+
+#endif /* RTE_COMPONENTS_H */

RTE/_Release_CS320/RTE_Components.h

@@ -0,0 +1,42 @@
+/*
+ * CSOLUTION generated file: DO NOT EDIT!
+ * Generated by: csolution version 2.7.0
+ *
+ * Project: 'Hello.Release+CS320' 
+ * Target:  'Release+CS320' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File: 
+ */
+#define CMSIS_device_header "SSE320.h"
+
+/* ARM::CMSIS Driver:[email protected] */
+#define RTE_USART0      1
+
+/* ARM::CMSIS-Compiler:STDERR:[email protected] */
+#define RTE_CMSIS_Compiler_STDERR                /* CMSIS-Compiler STDERR */
+#define RTE_CMSIS_Compiler_STDERR_Custom         /* CMSIS-Compiler STDERR: Custom */
+/* ARM::CMSIS-Compiler:STDIN:[email protected] */
+#define RTE_CMSIS_Compiler_STDIN                 /* CMSIS-Compiler STDIN */
+#define RTE_CMSIS_Compiler_STDIN_Custom          /* CMSIS-Compiler STDIN: Custom */
+/* ARM::CMSIS-Compiler:STDOUT:[email protected] */
+#define RTE_CMSIS_Compiler_STDOUT                /* CMSIS-Compiler STDOUT */
+#define RTE_CMSIS_Compiler_STDOUT_Custom         /* CMSIS-Compiler STDOUT: Custom */
+/* ARM::CMSIS:RTOS2:Keil RTX5&[email protected] */
+#define RTE_CMSIS_RTOS2                 /* CMSIS-RTOS2 */
+#define RTE_CMSIS_RTOS2_RTX5            /* CMSIS-RTOS2 Keil RTX5 */
+#define RTE_CMSIS_RTOS2_RTX5_SOURCE     /* CMSIS-RTOS2 Keil RTX5 Source */
+/* ARM::Device:Native Driver:[email protected] */
+#define RTE_MPS3_IO      1
+/* ARM::Device:Native Driver:[email protected] */
+#define RTE_SYSCOUNTER      1
+/* ARM::Device:Native Driver:[email protected] */
+#define RTE_TIMEOUT      1
+
+
+#endif /* RTE_COMPONENTS_H */