Merge pull request #7 from Evagan2018/main

Added support for Corestone_320

Author: vovamarch

.github/workflows/hello-ci.yml

@@ -33,7 +33,8 @@ jobs:
           {type: CM33_FP,   model: FVP_MPS2_Cortex-M33,     uart: fvp_mps2.UART0}, 
           {type: CS300,     model: FVP_Corstone_SSE-300,    uart: mps3_board.uart0},
           {type: CS310,     model: FVP_Corstone_SSE-310,    uart: mps3_board.uart0},
-          {type: CS315,     model: FVP_Corstone_SSE-315,    uart: mps4_board.uart0} 
+          {type: CS315,     model: FVP_Corstone_SSE-315,    uart: mps4_board.uart0},
+          {type: CS320,     model: FVP_Corstone_SSE-320,    uart: mps4_board.uart0}          
         ]
         build: [ 
           {type: Release},

FVP/FVP_Corstone_SSE-320/fvp_config.txt

@@ -0,0 +1,7 @@
+# Parameters:
+# instance.parameter=value       #(type, mode) default = 'def value' : description : [min..max]
+#---------------------------------------------------------------------------------------------------
+mps4_board.visualisation.disable-visualisation=1      # (bool  , init-time) default = '0'          : Enable/disable visualisation
+vis_hdlcd.disable_visualisation=1                     # (bool  , init-time) default = '0'          : Enable/disable visualisation
+mps4_board.uart0.shutdown_on_eot=1                    # (bool  , init-time) default = '0'          : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available)
+#---------------------------------------------------------------------------------------------------

Hello.cbuild-pack.yml

@@ -12,6 +12,9 @@ cbuild-pack:
     - resolved-pack: ARM::[email protected]
       selected-by-pack:
         - ARM::SSE_315_BSP
+    - resolved-pack: ARM::[email protected]
+      selected-by-pack:
+        - ARM::SSE_320_BSP
     - resolved-pack: ARM::[email protected]
       selected-by-pack:
         - ARM::V2M_MPS3_SSE_300_BSP

Hello.cproject.yml

@@ -19,36 +19,42 @@ project:
       - +CS300
       - +CS310
       - +CS315
+      - +CS320
 
     - component: Device:Native Driver:UART
       for-context:
       - +CS300
       - +CS310
       - +CS315
+      - +CS320
 
     - component: Device:Native Driver:SysCounter
       for-context:
       - +CS300
       - +CS310
       - +CS315
+      - +CS320
 
     - component: Device:Native Driver:SysTimer
       for-context:
       - +CS300
       - +CS310
       - +CS315
+      - +CS320
 
     - component: Device:Native Driver:Timeout
       for-context:
       - +CS300
       - +CS310
       - +CS315
+      - +CS320
 
     - component: Device:Definition
       for-context:
       - +CS300
       - +CS310
       - +CS315
+      - +CS320
 
   # List of source groups and files added to a project or a layer.
   groups:

Hello.csolution.yml

@@ -16,7 +16,8 @@ solution:
     - pack: ARM::CMSIS-RTX
     - pack: ARM::V2M_MPS3_SSE_300_BSP          # Corstone-300 (Cortex-M55)
     - pack: ARM::V2M_MPS3_SSE_310_BSP          # SSE-310-MPS3_FVP
-    - pack: ARM::SSE_315_BSP                   # SSE-315-FVP
+    - pack: ARM::SSE_315_BSP                   # SSE-315-FVP
+    - pack: ARM::SSE_320_BSP                   # SSE-320-FVP    
     - pack: Keil::V2M-MPS2_CMx_BSP             # For Cortex-M0 .. M33  ;  AVH-CM* devices.
     - pack: Keil::V2M-MPS2_IOTKit_BSP          # For the IOTKit_CM23_VHT, IOTKit_CM33_VHT, and IOTKit_CM33_FP_VHT devices
     - pack: Keil::V2M-MPS3_IOTKit_BSP          # For the IOTKit_CM33_MPS3 and the IOTKit_CM33_FP_MPS3 devices
@@ -33,6 +34,9 @@ solution:
     - type: CS315
       device: ARM::SSE-315-FVP
 
+    - type: CS320
+      device: ARM::SSE-320-FVP
+
     - type: CM0plus
       device: ARM::CMSDK_CM0plus_VHT
 

RTE/Device/SSE-320-FVP/ac6_linker_script.sct.src

@@ -0,0 +1,109 @@
+/*
+ * Copyright (c) 2023 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* ----------------------------------------------------------------------------
+  Stack seal size definition
+ *----------------------------------------------------------------------------*/
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define __STACKSEAL_SIZE 8
+#else
+#define __STACKSEAL_SIZE 0
+#endif
+
+/*----------------------------------------------------------------------------
+  Scatter File Definitions definition
+ *----------------------------------------------------------------------------*/
+
+LR_ROM0 __ROM0_BASE __ROM0_SIZE  {
+
+  ER_ROM0 __ROM0_BASE __ROM0_SIZE {
+    *.o (RESET, +First)
+    *(InRoot$$Sections)
+    *(+RO +XO)
+  }
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+  ER_CMSE_VENEER AlignExpr(+0, 32) (__ROM0_SIZE - AlignExpr(ImageLength(ER_ROM0), 32)) {
+    *(Veneer$$CMSE)
+  }
+#endif
+
+  RW_NOINIT __RAM0_BASE UNINIT (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE - __STACKSEAL_SIZE) {
+    *.o(.bss.noinit)
+    *.o(.bss.noinit.*)
+  }
+
+  RW_RAM0 AlignExpr(+0, 8) (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE - __STACKSEAL_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) {
+    *(+RW +ZI)
+  }
+
+#if __HEAP_SIZE > 0
+  ARM_LIB_HEAP  (AlignExpr(+0, 8)) EMPTY __HEAP_SIZE  {   ; Reserve empty region for heap
+  }
+#endif
+
+  ARM_LIB_STACK (__RAM0_BASE + __RAM0_SIZE - __STACKSEAL_SIZE) EMPTY -__STACK_SIZE {   ; Reserve empty region for stack
+  }
+
+#if __STACKSEAL_SIZE > 0
+  STACKSEAL +0 EMPTY __STACKSEAL_SIZE {             ; Reserve empty region for stack seal immediately after stack
+  }
+#endif
+
+#if __RAM1_SIZE > 0
+  RW_RAM1 __RAM1_BASE __RAM1_SIZE  {
+   .ANY (+RW +ZI)
+  }
+#endif
+
+#if __RAM2_SIZE > 0
+  RW_RAM2 __RAM2_BASE __RAM2_SIZE  {
+   .ANY (+RW +ZI)
+  }
+#endif
+
+#if __RAM3_SIZE > 0
+  RW_RAM3 __RAM3_BASE __RAM3_SIZE  {
+   .ANY (+RW +ZI)
+  }
+#endif
+}
+
+#if __ROM1_SIZE > 0
+LR_ROM1 __ROM1_BASE __ROM1_SIZE  {
+  ER_ROM1 +0 __ROM1_SIZE {
+   .ANY (+RO +XO)
+  }
+}
+#endif
+
+#if __ROM2_SIZE > 0
+LR_ROM2 __ROM2_BASE __ROM2_SIZE  {
+  ER_ROM2 +0 __ROM2_SIZE {
+   .ANY (+RO +XO)
+  }
+}
+#endif
+
+#if __ROM3_SIZE > 0
+LR_ROM3 __ROM3_BASE __ROM3_SIZE  {
+  ER_ROM3 +0 __ROM3_SIZE {
+   .ANY (+RO +XO)
+  }
+}
+#endif