Updated from Andy Pickard’s feedback

Author: stephentheobald-arm

content/learning-paths/cross-platform/sme/ZA.png

@@ -2,14 +2,14 @@
 review:
     - questions:
         question: >
-            What is the size of the ZA storage?
+            What are the supported sizes for the ZA storage in SME?
         answers:
-            - SVL x SVL bits
-            - SVL x SVL bytes
-            - SVL x SVL floats
-        correct_answer: 1
+            - 16x16, 32x32, 64x64, 128x128, and 256x256 bits
+            - 16x16, 32x32, 64x64, 128x128, and 256x256 bytes
+            - 16x16, 32x32, 64x64, 128x128, and 256x256 floats
+        correct_answer: 2
         explanation: >
-            The ZA storage is a two-dimensional array of SVL x SVL bits, where SVL (the Effective Streaming SVE Vector Length), is a power of two in the range 128 to 2048 bits.
+            The ZA storage is two-dimensional array of 8-bit elements, a power of two in the range 16 to 256 bytes.
 
     - questions:
         question: >

content/learning-paths/cross-platform/sme/_review.md

@@ -6,7 +6,7 @@ weight: 2
 layout: learningpathall
 ---
 
-The [Scalable Matrix Extension](https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/scalable-matrix-extension-armv9-a-architecture) (`SME`) is a system solution consisting of hardware and software components to efficiently process matrices, including matrix tile storage and outer-product operations.
+The [Scalable Matrix Extension](https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/scalable-matrix-extension-armv9-a-architecture) (SME) is a system solution consisting of hardware and software components to efficiently process matrices, including matrix tile storage and outer-product operations.
 
 SME introduces:
 * A register array storage ("ZA") capable of holding two-dimensional matrix tiles.
@@ -15,12 +15,14 @@ SME introduces:
 * Instructions that transfer a vector to or from a tile row or column.
 * System registers and fields that identify the presence and capabilities of SME, and enable and control its behavior at each Exception level.
 
-The ZA storage is two-dimensional array of SVL x SVL bits, where SVL (the Effective Streaming SVE Vector Length), is a power of two in the range 128 to 2048 bits.
-The ZA array can be accessed as vectors of 8-bit, 16-bit, 32-bit, 64-bit, or 128-bit elements, or as vectors of SVL bits.
-The ZA array can also be accessed as tiles.  A tile is a square, two-dimensional sub-array of elements within the ZA array.  
-A ZA tile can be accessed as vectors of 8-bit, 16-bit, 32-bit, 64-bit, or 128-bit elements, or as horizontal or vertical slices of SVL bits.
+The ZA storage is a two-dimensional array of SVL{{< sub "B" >}} x SVL{{< sub "B" >}} bytes, where SVL{{< sub "B" >}} is the number of 8-bit elements, a power of two in the range 16 to 256 bytes.
+The ZA array can be accessed as vectors of SVL bits, with element sizes 8-bit, 16-bit, 32-bit, 64-bit, or 128-bit.
 
-![example image alt-text#center](ZA.png "Figure 1. The ZA storage, shown for SVL=256 bits, organised as 32-bit floats, and the mapping to horizontal and vertical slices of ZA0-3 tiles")
+The ZA array can also be accessed as tiles.  A ZA tile is a square, two-dimensional sub-array of elements within the ZA array, and can be accessed as vectors of 8-bit, 16-bit, 32-bit, 64-bit, or 128-bit elements.
+A ZA tile slice is a one-dimensional set of horizontally or vertically contiguous elements within a ZA tile.
+
+![example image alt-text#center](ZA.png "Figure 1. The ZA storage, shown for SVL{{< sub "B" >}} = 32, organized as 32-bit floats, and the mapping to horizontal and vertical slices of ZA0-3 tiles.
+In this arrangement, there are SVL{{< sub "B" >}} = 32 rows, and SVL{{< sub "S" >}} = 8 columns of 32-bit elements.")
 
 The Scalable Matrix Extension version 2 (SME2) extends the SME architecture to increase the number of applications that can benefit from the computational efficiency of SME, beyond its initial focus on outer products and matrix-matrix multiplication.  SME2 adds:
 * Data processing instructions with multi-vector operands and a multi-vector predication mechanism.
@@ -32,4 +34,3 @@ The new instructions enable SME2 to accelerate more workloads than the original
 
 SME is represented by the architectural feature FEAT_SME.  FEAT_SME is an optional extension from Armv9.2-A.
 SME2 is represented by the architectural feature FEAT_SME2.  FEAT_SME2 is an optional extension from Armv9.2-A.  FEAT_SME2 requires FEAT_SME.
-