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Merge pull request #2399 from jasonrandrews/review
Update topdown-tool output
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‎content/learning-paths/cross-platform/topdown-compare/2-code-examples.md‎

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@@ -153,11 +153,17 @@ The output is similar to:
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```output
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Performing 1000000000 dependent floating-point divisions...
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Monitoring command: test. Hit Ctrl-C to stop.
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Run 1
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Done. Final result: 0.000056
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Stage 2 (uarch metrics)
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=======================
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[General]
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Instructions Per Cycle 0.355 per cycle
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CPU Neoverse V2 metrics
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└── Stage 2 (uarch metrics)
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└── General (General)
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└── ┏━━━━━━━━━━━━━━━━━━━━━━━━┳━━━━━━━┳━━━━━━━━━━━┓
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┃ Metric ┃ Value ┃ Unit ┃
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┡━━━━━━━━━━━━━━━━━━━━━━━━╇━━━━━━━╇━━━━━━━━━━━┩
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│ Instructions Per Cycle │ 0.324 │ per cycle │
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└────────────────────────┴───────┴───────────┘
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```
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Collect the Stage 1 topdown metrics using Arm's cycle accounting:
@@ -170,12 +176,18 @@ The output is similar to:
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```output
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Performing 1000000000 dependent floating-point divisions...
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Monitoring command: test. Hit Ctrl-C to stop.
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Run 1
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Done. Final result: 0.000056
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Stage 1 (Topdown metrics)
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=========================
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[Cycle Accounting]
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Frontend Stalled Cycles 0.04% cycles
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Backend Stalled Cycles. 88.15% cycles
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CPU Neoverse V2 metrics
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└── Stage 2 (uarch metrics)
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└── Cycle Accounting (Cycle_Accounting)
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└── ┏━━━━━━━━━━━━━━━━━━━━━━━━━┳━━━━━━━┳━━━━━━┓
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┃ Metric ┃ Value ┃ Unit ┃
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┡━━━━━━━━━━━━━━━━━━━━━━━━━╇━━━━━━━╇━━━━━━┩
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│ Backend Stalled Cycles │ 93.22 │ % │
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│ Frontend Stalled Cycles │ 0.03 │ % │
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└─────────────────────────┴───────┴──────┘
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```
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This confirms the example has high backend stalls, equivalent to x86's Backend_Bound category. Notice how Arm's Stage 1 uses percentage of cycles rather than Intel's slot-based accounting.
@@ -192,12 +204,20 @@ The output is similar to:
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```output
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Performing 1000000000 dependent floating-point divisions...
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Monitoring command: test. Hit Ctrl-C to stop.
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Run 1
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Done. Final result: 0.000056
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Stage 2 (uarch metrics)
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=======================
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[L1 Data Cache Effectiveness]
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L1D Cache MPKI............... 0.023 misses per 1,000 instructions
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L1D Cache Miss Ratio......... 0.000 per cache access
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CPU Neoverse V2 metrics
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└── Stage 2 (uarch metrics)
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└── L1 Data Cache Effectiveness (L1D_Cache_Effectiveness)
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├── Follows
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│ └── Backend Bound (backend_bound)
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└── ┏━━━━━━━━━━━━━━━━━━━━━━┳━━━━━━━┳━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━┓
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┃ Metric ┃ Value ┃ Unit ┃
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┡━━━━━━━━━━━━━━━━━━━━━━╇━━━━━━━╇━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━┩
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│ L1D Cache Miss Ratio │ 0.000 │ per cache access │
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│ L1D Cache MPKI │ 0.129 │ misses per 1,000 instructions │
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└──────────────────────┴───────┴───────────────────────────────┘
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```
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For L1 instruction cache effectiveness:
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```output
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Performing 1000000000 dependent floating-point divisions...
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Monitoring command: test. Hit Ctrl-C to stop.
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Run 1
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Done. Final result: 0.000056
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Stage 2 (uarch metrics)
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=======================
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[L1 Instruction Cache Effectiveness]
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L1I Cache MPKI............... 0.022 misses per 1,000 instructions
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L1I Cache Miss Ratio......... 0.000 per cache access
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CPU Neoverse V2 metrics
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└── Stage 2 (uarch metrics)
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└── L1 Instruction Cache Effectiveness (L1I_Cache_Effectiveness)
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├── Follows
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│ └── Frontend Bound (frontend_bound)
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└── ┏━━━━━━━━━━━━━━━━━━━━━━┳━━━━━━━┳━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━┓
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┃ Metric ┃ Value ┃ Unit ┃
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┡━━━━━━━━━━━━━━━━━━━━━━╇━━━━━━━╇━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━┩
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│ L1I Cache Miss Ratio │ 0.003 │ per cache access │
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│ L1I Cache MPKI │ 0.474 │ misses per 1,000 instructions │
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└──────────────────────┴───────┴───────────────────────────────┘
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```
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For last level cache:
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```output
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Performing 1000000000 dependent floating-point divisions...
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Monitoring command: test. Hit Ctrl-C to stop.
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Run 1
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Done. Final result: 0.000056
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Stage 2 (uarch metrics)
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=======================
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[Last Level Cache Effectiveness]
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LL Cache Read MPKI.............. 0.017 misses per 1,000 instructions
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LL Cache Read Miss Ratio........ 0.802 per cache access
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LL Cache Read Hit Ratio......... 0.198 per cache access
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CPU Neoverse V2 metrics
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└── Stage 2 (uarch metrics)
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└── Last Level Cache Effectiveness (LL_Cache_Effectiveness)
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├── Follows
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│ ├── Backend Bound (backend_bound)
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│ └── Frontend Bound (frontend_bound)
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└── ┏━━━━━━━━━━━━━━━━━━━━━━━━━━┳━━━━━━━┳━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━┓
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┃ Metric ┃ Value ┃ Unit ┃
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┡━━━━━━━━━━━━━━━━━━━━━━━━━━╇━━━━━━━╇━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━┩
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│ LL Cache Read Hit Ratio │ nan │ per cache access │
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│ LL Cache Read Miss Ratio │ nan │ per cache access │
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│ LL Cache Read MPKI │ 0.000 │ misses per 1,000 instructions │
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└──────────────────────────┴───────┴───────────────────────────────┘
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```
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For operation mix:
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```output
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Performing 1000000000 dependent floating-point divisions...
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Monitoring command: test. Hit Ctrl-C to stop.
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Run 1
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Done. Final result: 0.000056
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Stage 2 (uarch metrics)
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=======================
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[Speculative Operation Mix]
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Load Operations Percentage.......... 16.70% operations
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Store Operations Percentage......... 16.59% operations
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Integer Operations Percentage....... 33.61% operations
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Advanced SIMD Operations Percentage. 0.00% operations
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Floating Point Operations Percentage 16.45% operations
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Branch Operations Percentage........ 16.65% operations
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Crypto Operations Percentage........ 0.00% operations
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CPU Neoverse V2 metrics
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└── Stage 2 (uarch metrics)
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└── Speculative Operation Mix (Operation_Mix)
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├── Follows
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│ ├── Backend Bound (backend_bound)
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│ └── Retiring (retiring)
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└── ┏━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━┳━━━━━━━┳━━━━━━┓
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┃ Metric ┃ Value ┃ Unit ┃
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┡━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━╇━━━━━━━╇━━━━━━┩
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│ Barrier Operations Percentage │ ❌ │ % │
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│ Branch Operations Percentage │ ❌ │ % │
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│ Crypto Operations Percentage │ 0.00 │ % │
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│ Integer Operations Percentage │ 33.52 │ % │
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│ Load Operations Percentage │ 16.69 │ % │
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│ Floating Point Operations Percentage │ 16.51 │ % │
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│ Advanced SIMD Operations Percentage │ 0.00 │ % │
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│ Store Operations Percentage │ 16.58 │ % │
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│ SVE Operations (Load/Store Inclusive) Percentage │ 0.00 │ % │
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└──────────────────────────────────────────────────┴───────┴──────┘
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```
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