First review of FVP Learning Path

Author: jasonrandrews

content/learning-paths/embedded-and-microcontrollers/linux-on-fvp/1-Intro.md

@@ -6,33 +6,33 @@ weight: 2
 layout: learningpathall
 ---
 
-Arm Ecosystem Fixed Virtual Platforms (FVPs) model hardware subsystems target different market segments and applications.
+Arm Ecosystem Fixed Virtual Platforms (FVPs) model hardware subsystems and target different market segments and applications.
 
-FVPs use binary translation technology to deliver fast, functional simulations of Arm-based systems, including processor, memory, and peripherals. They implement a programmer's view suitable for software development and enable execution of full software stacks, providing a widely available platform ahead of silicon.
+FVPs use binary translation technology to deliver fast, functional simulations of Arm-based systems, including processor, memory, and peripherals. They implement a programmer's view suitable for software development and enable execution of full software stacks, providing an available platform to run software before silicon is available.
 
-Arm provides different types of FVPs. There are several freely available, pre-built Armv8‑A FVPs for download from [Arm Ecosystem Models](https://developer.arm.com/Tools%20and%20Software/Fixed%20Virtual%20Platforms) on Arm Developer website. You can use these FVPs without a license. For example, the AEMv8-A Base Platform RevC FVP is freely available, and it supports the latest Armv8‑A architecture versions up to v8.7 and Armv9-A.
+Arm provides two different types of FVPs. 
 
-The [Arm reference software stack](https://gitlab.arm.com/arm-reference-solutions/arm-reference-solutions-docs/-/blob/master/docs/aemfvp-a/user-guide.rst) is based on the above RevC model. However, some Armv8 FVPs with a fixed number of cores are replaced by FVPs with a configurable number of cores, for example:
+## Arm Ecosystem FVPs
 
-* FVP_Base_Cortex-A55x4
-* FVP_Base_Cortex-A78x4
-* FVP_Base_Cortex-X1x4
-* FVP_Base_Cortex-X2x4
-* FVP_Base_Cortex-A78AEx2
-* FVP_Base_Cortex-A76x4
-* FVP_Base_Neoverse-N2x1
-* FVP_Base_Neoverse-N1x4
-* FVP_Base_Cortex-A510x4
-* FVP_Base_Cortex-A53x4
-* FVP_Base_Cortex-A76x4
+There are several freely available, pre-built Armv8‑A FVPs for download from [Arm Ecosystem Models](https://developer.arm.com/Tools%20and%20Software/Fixed%20Virtual%20Platforms#Downloads) on the Arm Developer website. You can use these FVPs without a license. 
 
-### Set up the environment
+There are multiple categories of Ecosystem FVPs such as:
+- Architecture FVPs
+- Automotive FVPs
+- Infrastructure FVPs
+- IoT FVPs
+
+For example, in the architecture category, the AEMv8-A Base Platform RevC FVP is freely available, and it supports the latest Armv8‑A architecture versions up to v8.7 and Armv9-A.
+
+The [Arm reference software stack](https://gitlab.arm.com/arm-reference-solutions/arm-reference-solutions-docs/-/blob/master/docs/aemfvp-a/user-guide.rst) is based on the above RevC model. 
 
-The [Arm reference software](https://gitlab.arm.com/arm-reference-solutions/arm-reference-solutions-docs/-/blob/master/docs/aemfvp-a/user-guide.rst) stack is the codebase. Follow the [Armv-A Base AEM FVP Platform Software User Guide](https://gitlab.arm.com/arm-reference-solutions/arm-reference-solutions-docs/-/blob/master/docs/aemfvp-a/user-guide.rst) to set up the environment, download the software stack, and get the toolchain.
+## Arm Base FVPs specific CPU types
 
-he FVP_Base_Cortex-\<xxx> FVP is available for you to build and run Linux host environments. Contact Arm Support [[email protected]](mailto:[email protected]) to request access.
+Arm Base Armv8-A FVPs with specific CPU types are configured with a fixed number of cores. These are also called CPU FVPs because they specify the CPU types instead of the architecture version.
 
-This document supports running the software stack on the following FVPs:
+The FVP_Base_Cortex-\<xxx> FVP is available for you to build and run on Linux computers. Contact Arm Support [[email protected]](mailto:[email protected]) to request access.
+
+You can use any of the FVPs listed below to run the reference software stack: 
 
 * FVP_Base_Cortex-A510x4
 * FVP_Base_Cortex-A510x4+Cortex-A710x4
@@ -68,9 +68,9 @@ This document supports running the software stack on the following FVPs:
 * FVP_Base_Neoverse-E1x4
 * FVP_Base_Neoverse-N1x4
 
-However, this is not a full list. This blog might apply to more FVP platforms, but no test is done for these platforms, for example:
+### Set up the environment
+
+This Learning Path uses the [Arm reference software](https://gitlab.arm.com/arm-reference-solutions/arm-reference-solutions-docs/-/blob/master/docs/aemfvp-a/user-guide.rst) stack.
+
+Follow the [Armv-A Base AEM FVP Platform Software User Guide](https://gitlab.arm.com/arm-reference-solutions/arm-reference-solutions-docs/-/blob/master/docs/aemfvp-a/user-guide.rst) to set up the environment, download the software stack, and get the toolchain.
 
-* FVP_Base_Cortex-A55x1
-* FVP_Base_Cortex-A55x2
-* FVP_Base_Cortex-A55x1+Cortex-A75x1
-* FVP_Base_Cortex-A55x4+Cortex-A76x2

content/learning-paths/embedded-and-microcontrollers/linux-on-fvp/2-Setup.md

@@ -1,22 +1,35 @@
 ---
 title: Use TF-A extra build options to build cpu_ops into images
-weight: 4
+weight: 3
 
 ### FIXED, DO NOT MODIFY
 layout: learningpathall
 ---
 
-### 1. Why build cpu_ops into images
+## What are cpu_ops?
+
+In the context of Arm Trusted Firmware-A (TF-A), cpu_ops refers to a framework that defines CPU-specific operations essential for managing power states and initialization sequences. This framework is particularly crucial for implementing the Power State Coordination Interface (PSCI), which standardizes power management in Arm systems.  
+
+## What is the purpose of cpu_ops?
+
+The cpu_ops framework provides a set of function pointers tailored to specific CPU architectures. These functions handle operations such as:
+	•	Reset Handling: Executing CPU-specific reset sequences.
+	•	Power Management: Managing CPU power-down and power-up sequences.
+	•	Errata Workarounds: Applying necessary workarounds for known CPU errata during initialization.
+
+By abstracting these operations, TF-A can support multiple CPU types seamlessly, allowing for a modular and maintainable codebase.
+
+## Why build cpu_ops into images?
 
 If you build the software without any modification, you might get the following error message after running the software stack:
 
-```
+```console
 ASSERT: File lib/cpus/aarch64/cpu_helpers.S Line 00035
 ```
 
-The previous error message is issued because the TF-A does not build the cpu_ops into the images:
+The previous error message occurs because the TF-A does not build the cpu_ops into the images:
 
-```
+```console
 31   /* Get the matching cpu_ops pointer */
 
 32   bl   get_cpu_ops_ptr
@@ -33,7 +46,7 @@ The previous error message is issued because the TF-A does not build the cpu_ops
 
 The cpu_ops are defined in the source file as follows:
 
-```
+```console
 lib/cpus/aarch64/cortex_a510.S
 lib/cpus/aarch64/cortex_a53.S
 lib/cpus/aarch64/cortex_a55.S
@@ -46,9 +59,11 @@ lib/cpus/aarch64/cortex_a72.S
 lib/cpus/aarch64/cortex_a73.S
 ```
 
-Check the Makefile (plat/arm/board/fvp/platform.mk) of the FVP platform. You can find the following code:  
+Check the Makefile (plat/arm/board/fvp/platform.mk) of the FVP platform. 
 
-```
+Find the following code:  
+
+```console
 ifeq (${HW_ASSISTED_COHERENCY}, 0)
 # Cores used without DSU
 	FVP_CPU_LIBS	+=	lib/cpus/aarch64/cortex_a35.S			\
@@ -89,9 +104,9 @@ else
 endif
 ```
 
-HW_ASSISTED_COHERENCY = 0 and CTX_INCLUDE_AARCH32_REGS =1 are default build options.
+Default build options are `HW_ASSISTED_COHERENCY = 0` and `CTX_INCLUDE_AARCH32_REGS = 1`.
 
-### 2. Required build options
+### What are the required build options to fix the problem?
 
 Building the cpu_ops into the TF-A image requires different build options, depending on the CPU type. For example, different platforms require different build options when building the TF-A:
 
@@ -101,42 +116,35 @@ Building the cpu_ops into the TF-A image requires different build options, depen
 
 Note: The build option USE_COHERENT_MEM cannot be enabled with HW_ASSISTED_COHERENCY=1.
 
-
-### 3. Steps to build cpu_ops into the TF-A image
+### What are the steps to build cpu_ops into the TF-A image?
 
 Perform the following steps to build cpu_ops into the TF-A image:
 
-3.1  Modify the following build script to add build options. The [Arm reference software stack](https://gitlab.arm.com/arm-reference-solutions/arm-reference-solutions-docs/-/blob/master/docs/aemfvp-a/user-guide.rst) uses the [build-scripts](https://gitlab.arm.com/arm-reference-solutions/build-scripts) to build the TF-A.
+Modify the following build script to add build options. The [Arm reference software stack](https://gitlab.arm.com/arm-reference-solutions/arm-reference-solutions-docs/-/blob/master/docs/aemfvp-a/user-guide.rst) uses the [build-scripts](https://gitlab.arm.com/arm-reference-solutions/build-scripts) to build the TF-A.
 
-```
-build-scripts/ configs/aemfvp-a/aemfvp-a
-```
-
-3.2 Add TF-A build options, depending on the CPU type. For example:
+Add TF-A build options, depending on the CPU type. For example:
 
 * For A55 CPU FVP, add the following line:
 
-```
+```console
 ARM_TF_BUILD_FLAGS="$ARM_TF_BUILD_FLAGS HW_ASSISTED_COHERENCY=1 USE_COHERENT_MEM=0 "
 ```
 
 * For A78 CPU FVP, add the following line:
 
-```
+```console
 ARM_TF_BUILD_FLAGS="$ARM_TF_BUILD_FLAGS HW_ASSISTED_COHERENCY=1 USE_COHERENT_MEM=0 CTX_INCLUDE_AARCH32_REGS=0"
 ```
 
-3.3  Rebuild the TF-A by using the following commands:
+Rebuild the TF-A by using the following commands:
 
-```
+```console
 ./build-scripts/build-arm-tf.sh -p aemfvp-a -f busybox clean
-
 ./build-scripts/build-arm-tf.sh -p aemfvp-a -f busybox build
 ```
 
-3.4 Package the built TF-A into the BusyBox disk image by using the following command:
+Package the built TF-A into the BusyBox disk image by using the following command:
 
-```
+```console
 ./build-scripts/aemfvp-a/build-test-busybox.sh -p aemfvp-a package
 ```
-