Removed diagram and accompanying reference

Author: madeline-underwood

content/learning-paths/servers-and-cloud-computing/arm-cpp-memory-model/1.md

@@ -36,12 +36,6 @@ MULT R3, #R1, #5 // B
 
 4. **Hardware Perceived Order** - this is the perspective observed by other devices in the system, which can differ if the hardware buffers writes or merges memory operations. Crucially, the hardware-perceived order can vary between CPU architectures, for example between x86 and Arm, and this should be considered when porting applications. 
 
-An abstract diagram from the academic paper is shown below ["A Tutorial Introduction to the ARM and POWER Relaxed Memory Models" Maranget et. al, 2012]. 
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-A write operation in one of the five threads in the pentagon below might propagate to the other threads in any order. 
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-!["Multi-copy Atomic Model" abstract_model](./multi-copy-atomic.png)
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 ## High-level differences between the Arm Memory Model and the x86 Memory Model
 
 The memory models of Arm and x86 architectures differ in terms of ordering guarantees and required synchronizations.