Corrected figure numbers

Author: stephentheobald-arm

content/learning-paths/cross-platform/sme/matrix-multiply-example.md

@@ -51,7 +51,7 @@ Execution can be controlled by the `Debug Control` pane icon bar (eg `Step Instr
 
 ## Understand the example
 
-![example image alt-text#center](armds_sme2.png "Figure 1. Debugging the SME2 example in Arm Development Studio")
+![example image alt-text#center](armds_sme2.png "Figure 2. Debugging the SME2 example in Arm Development Studio")
 
 1. In the Registers view, expand AArch64 > System > ID > ID_AA64PFR1_EL1. Notice the SME bits are set to 2, meaning the SME2 architectural state and programmers model are implemented on this target.
 2. This bit can also be inspected in the Commands view, by entering `output $AArch64::$System::$ID::$ID_AA64PFR1_EL1.SME`. Other bits in other registers may be inspected similarly.

content/learning-paths/cross-platform/sme/sme-intro.md

@@ -20,7 +20,7 @@ The ZA array can be accessed as vectors of 8-bit, 16-bit, 32-bit, 64-bit, or 128
 The ZA array can also be accessed as tiles.  A tile is a square, two-dimensional sub-array of elements within the ZA array.  
 A ZA tile can be accessed as vectors of 8-bit, 16-bit, 32-bit, 64-bit, or 128-bit elements, or as horizontal or vertical slices of SVL bits.
 
-![example image alt-text#center](ZA.png "Figure 1. The ZA storage, shown for SVL=256 bits, organised as 32-bit floats, and the mapping of horizontal and vertical slices to ZA0-3 tiles")
+![example image alt-text#center](ZA.png "Figure 1. The ZA storage, shown for SVL=256 bits, organised as 32-bit floats, and the mapping to horizontal and vertical slices of ZA0-3 tiles")
 
 The Scalable Matrix Extension version 2 (SME2) extends the SME architecture to increase the number of applications that can benefit from the computational efficiency of SME, beyond its initial focus on outer products and matrix-matrix multiplication.  SME2 adds:
 * Data processing instructions with multi-vector operands and a multi-vector predication mechanism.