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Copy file name to clipboardExpand all lines: content/learning-paths/cross-platform/simd-info-demo/simdinfo-description.md
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@@ -64,12 +64,4 @@ When you need to port code from one architecture to another, the advanced search
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Furthermore, **SIMD.info**’s comparison tools enhance this process by enabling side-by-side comparisons of instructions from various platforms. This feature highlights the similarities and differences between instructions, which is crucial for accurately adapting your code. By understanding how similar operations are implemented across architectures, you can ensure that your ported code performs optimally.
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Let's look at an actual example.
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<!-- IMAGE HERE:
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 -->
You can see that the results are the same as in the **SSE4.2** example.
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{{% notice Note %}}
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We initialized the vectors in reverse order compared to the **SSE4.2** version because **{}** bracket initialization loads vectors from LSB to MSB, whereas **`_mm_set_ps`** loads the elements MSB to LSB.
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{{% /notice %}}
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You can see that the results are the same as in the **SSE4.2** example.
// adding them as 16-bit signed integers -> -23336 (overflow!)
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The output should look like:
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```output
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a : 96 82 6e 5a 46 32 1e a
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b : a08c7864503c2814
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_mm_madd_epi16(a, b) : a4d8 0 56b8 0 2198 0 578 0
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a : a 1e 32 46 5a 6e 8296
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b : 14283c5064788ca0
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_mm_madd_epi16(a, b) : 578 0 2198 0 56b8 0 a4d8 0
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```
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You will note that the result of the first element is a negative number, even though we added 2 positive results (`130*140` and `150*160`). That is because the result of the addition has to occupy a 16-bit signed integer element and when the first is larger we have the effect of an negative overflow. The result is the same in binary arithmetic, but when interpreted into a signed integer, it turns the number into a negative.
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You will note that the result of the last element is a negative number, even though we added 2 positive results (`130*140` and `150*160`). That is because the result of the addition has to occupy a 16-bit signed integer element and when the first is larger we have the effect of an negative overflow. The result is the same in binary arithmetic, but when interpreted into a signed integer, it turns the number into a negative.
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The rest of the values are as expected. Notice how each pair has a zero element next to it. The results are correct, but they are not in the correct order. You could get the correct order in multiple ways, using the widening intrinsics **`vmovl`** to zero-extend or using the **`zip`** ones to merge with zero elements. The fastest way is the **`vmovl`**intrinsics, as you can see in the next example:
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The rest of the values are as expected. Notice how each pair has a zero element next to it. The results are correct, but they are not in the correct order. In this example, we chose to use vmovl to zero-extend values, which achieves the correct order with zero elements in place. While both vmovl and zip could be used for this purpose, we opted for **vmovl**in this implementation. For more details, see the ARM Software Optimization Guides, such as the [Neoverse V2 guide](https://developer.arm.com/documentation/109898/latest/).
As you can see the results of both match, **SIMD.info** was especially helpful in this process, providing detailed descriptions and examples that guided the translation of complex intrinsics between different SIMD architectures.
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