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ArnavionArnavion
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Implement MOP fusion in emulator.
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‎freestanding/riscv64-arnavion-none-elf.json‎

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"data-layout": "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128",
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"eh-frame-header": false,
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"emit-debug-gdb-scripts": false,
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"features": "+forced-atomics,+zba,+zbs,+zca,+zcb,+zicond,+zicsr,+zicntr",
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"features": "+forced-atomics,+zba,+zbs,+zca,+zcb,+zicond,+zicsr,+zicntr,+auipc-addi-fusion,+ld-add-fusion,+lui-addi-fusion",
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"linker": "rust-lld",
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"linker-flavor": "gnu-lld",
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"llvm-target": "riscv64",

‎tc/txt/alu.txt‎

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| remu rd, rs1, rs2 | 12 | 7 | 1 | | -> | rs1 | rs2 | %u |
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| remuw rd, rs1, rs2 | 14 | 7 | 1 | | -> | rs1uw | rs2uw | %uw |
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+---------------------------------+--------+--------+--------+--------+----+-------------+-------------+----------------+
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---
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Zarnavion (produced by MOP fusion)
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+---------------------------------+--------+--------+--------+--------+----+---------------------------+----------------+
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| inst | opcode | funct3 | funct7 | funct5 | -> | Misc | rd |
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| | | | | | -> | in3 | in4 | |
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+=================================+========+========+========+========+====+=============+=============+================+
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| abs rd, rs1 | 2 | 7 | 0 | | -> | rs1 | | abs |
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+---------------------------------+--------+--------+--------+--------+----+---------------------------+----------------+
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+---------------------------------+--------+--------+--------+--------+----+--------------------------+----------------+------+-------+---------+
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| inst | opcode | funct3 | funct7 | funct5 | -> | Adder | rd | RAM | RAM | RAM |
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| | | | | | -> | in1 | in2 | | Load | Store | Address |
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+=================================+========+========+========+========+====+===================+======+================+======+=======+=========+
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| lb.pc rd, imm(pc) | 2 | 0 | 0 | | -> | pc | imm | RAM Load Value | 1 | | + |
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| lh.pc rd, imm(pc) | 2 | 1 | 0 | | -> | pc | imm | RAM Load Value | 1 | | + |
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| lw.pc rd, imm(pc) | 2 | 2 | 0 | | -> | pc | imm | RAM Load Value | 1 | | + |
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| ld.pc rd, imm(pc) | 2 | 3 | 0 | | -> | pc | imm | RAM Load Value | 1 | | + |
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| lbu.pc rd, imm(pc) | 2 | 4 | 0 | | -> | pc | imm | RAM Load Value | 1 | | + |
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| lhu.pc rd, imm(pc) | 2 | 5 | 0 | | -> | pc | imm | RAM Load Value | 1 | | + |
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| lwu.pc rd, imm(pc) | 2 | 6 | 0 | | -> | pc | imm | RAM Load Value | 1 | | + |
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+---------------------------------+--------+--------+--------+--------+----+-------------------+------+----------------+------+-------+---------+
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| lb.add rd, rs2(rs1) | 2 | 0 | 1 | | -> | rs1 | rs2 | RAM Load Value | 1 | | + |
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| lh.add rd, rs2(rs1) | 2 | 1 | 1 | | -> | rs1 | rs2 | RAM Load Value | 1 | | + |
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| lw.add rd, rs2(rs1) | 2 | 2 | 1 | | -> | rs1 | rs2 | RAM Load Value | 1 | | + |
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| ld.add rd, rs2(rs1) | 2 | 3 | 1 | | -> | rs1 | rs2 | RAM Load Value | 1 | | + |
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| lbu.add rd, rs2(rs1) | 2 | 4 | 1 | | -> | rs1 | rs2 | RAM Load Value | 1 | | + |
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| lhu.add rd, rs2(rs1) | 2 | 5 | 1 | | -> | rs1 | rs2 | RAM Load Value | 1 | | + |
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| lwu.add rd, rs2(rs1) | 2 | 6 | 1 | | -> | rs1 | rs2 | RAM Load Value | 1 | | + |
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+---------------------------------+--------+--------+--------+--------+----+-------------------+------+----------------+------+-------+---------+
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| lb.sh1add rd, (rs1 << 1 + rs2) | 2 | 0 | 2 | | -> | rs1 << 1 | rs2 | RAM Load Value | 1 | | + |
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| lh.sh1add rd, (rs1 << 1 + rs2) | 2 | 1 | 2 | | -> | rs1 << 1 | rs2 | RAM Load Value | 1 | | + |
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| lw.sh1add rd, (rs1 << 1 + rs2) | 2 | 2 | 2 | | -> | rs1 << 1 | rs2 | RAM Load Value | 1 | | + |
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| ld.sh1add rd, (rs1 << 1 + rs2) | 2 | 3 | 2 | | -> | rs1 << 1 | rs2 | RAM Load Value | 1 | | + |
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| lbu.sh1add rd, (rs1 << 1 + rs2) | 2 | 4 | 2 | | -> | rs1 << 1 | rs2 | RAM Load Value | 1 | | + |
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| lhu.sh1add rd, (rs1 << 1 + rs2) | 2 | 5 | 2 | | -> | rs1 << 1 | rs2 | RAM Load Value | 1 | | + |
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| lwu.sh1add rd, (rs1 << 1 + rs2) | 2 | 6 | 2 | | -> | rs1 << 1 | rs2 | RAM Load Value | 1 | | + |
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+---------------------------------+--------+--------+--------+--------+----+-------------------+------+----------------+------+-------+---------+
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| lb.sh2add rd, (rs1 << 2 + rs2) | 2 | 0 | 3 | | -> | rs1 << 2 | rs2 | RAM Load Value | 1 | | + |
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| lh.sh2add rd, (rs1 << 2 + rs2) | 2 | 1 | 3 | | -> | rs1 << 2 | rs2 | RAM Load Value | 1 | | + |
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| lw.sh2add rd, (rs1 << 2 + rs2) | 2 | 2 | 3 | | -> | rs1 << 2 | rs2 | RAM Load Value | 1 | | + |
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| ld.sh2add rd, (rs1 << 2 + rs2) | 2 | 3 | 3 | | -> | rs1 << 2 | rs2 | RAM Load Value | 1 | | + |
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| lbu.sh2add rd, (rs1 << 2 + rs2) | 2 | 4 | 3 | | -> | rs1 << 2 | rs2 | RAM Load Value | 1 | | + |
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| lhu.sh2add rd, (rs1 << 2 + rs2) | 2 | 5 | 3 | | -> | rs1 << 2 | rs2 | RAM Load Value | 1 | | + |
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| lwu.sh2add rd, (rs1 << 2 + rs2) | 2 | 6 | 3 | | -> | rs1 << 2 | rs2 | RAM Load Value | 1 | | + |
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+---------------------------------+--------+--------+--------+--------+----+-------------------+------+----------------+------+-------+---------+
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| lb.sh3add rd, (rs1 << 3 + rs2) | 2 | 0 | 4 | | -> | rs1 << 3 | rs2 | RAM Load Value | 1 | | + |
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| lh.sh3add rd, (rs1 << 3 + rs2) | 2 | 1 | 4 | | -> | rs1 << 3 | rs2 | RAM Load Value | 1 | | + |
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| lw.sh3add rd, (rs1 << 3 + rs2) | 2 | 2 | 4 | | -> | rs1 << 3 | rs2 | RAM Load Value | 1 | | + |
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| ld.sh3add rd, (rs1 << 3 + rs2) | 2 | 3 | 4 | | -> | rs1 << 3 | rs2 | RAM Load Value | 1 | | + |
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| lbu.sh3add rd, (rs1 << 3 + rs2) | 2 | 4 | 4 | | -> | rs1 << 3 | rs2 | RAM Load Value | 1 | | + |
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| lhu.sh3add rd, (rs1 << 3 + rs2) | 2 | 5 | 4 | | -> | rs1 << 3 | rs2 | RAM Load Value | 1 | | + |
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| lwu.sh3add rd, (rs1 << 3 + rs2) | 2 | 6 | 4 | | -> | rs1 << 3 | rs2 | RAM Load Value | 1 | | + |
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+---------------------------------+--------+--------+--------+--------+----+-------------------+------+----------------+------+-------+---------+

‎tc/txt/mop-fusion.txt‎

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Refs:
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- https://arxiv.org/pdf/1607.02318
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- https://en.wikichip.org/wiki/macro-operation_fusion#RISC-V
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- https://github.com/llvm/llvm-project/blob/173907b5d77115623f160978a95159e36e05ee6c/llvm/lib/Target/RISCV/RISCVMacroFusion.td
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---
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Load immediate
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+---------------------------+-------------------------------------------------+--------------------------------------+
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| Instructions | Fusion condition | Fused instruction |
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+===========================+=================================================+======================================+
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| auipc rd_a, imm_a | rd_a == rd_b && rd_a == rs1_b | addi rd_b, x0, (imm_a + imm_b) |
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| addi rd_b, rs1_b, imm_b | | |
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+---------------------------+-------------------------------------------------+--------------------------------------+
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| lui rd_a, imm_a | rd_a == rd_b && rd_a == rs1_b && rs1_b != rs2_b | addi rd_a, rs2_b, imm_a |
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| add rd_b, rs1_b, rs2_b | | |
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+---------------------------+-------------------------------------------------+--------------------------------------+
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| lui rd_a, imm_a | rd_a == rd_b && rd_a == rs1_b | addi rd_b, x0, (imm_a + imm_b) |
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| addi rd_b, rs1_b, imm_b | | |
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+---------------------------+-------------------------------------------------+--------------------------------------+
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| lui rd_a, imm_a | rd_a == rd_b && rd_a == rs1_b | addiw rd_b, x0, (imm_a + imm_b) |
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| addiw rd_b, rs1_b, imm_b | | |
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+---------------------------+-------------------------------------------------+--------------------------------------+
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Op
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+---------------------------+-------------------------------------------------+--------------------------------------+
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| Instructions | Fusion condition | Fused instruction |
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+===========================+=================================================+======================================+
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| sub rd_a, x0, rs2_a | rd_a == rd_b && rd_a == rs1_b | abs rd_b, rs2_a |
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| max rd_b, rs1_b, rs2_b | | |
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+---------------------------+-------------------------------------------------+--------------------------------------+
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Jump
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+---------------------------+-------------------------------------------------+--------------------------------------+
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| Instructions | Fusion condition | Fused instruction |
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+===========================+=================================================+======================================+
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| auipc rd_a, imm_a | rd_a == rd_b && rd_a == rs1_b | jal rd_b, (imm_a + imm_b) |
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| jalr rd_b, imm_b(rs1_b) | | |
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+---------------------------+-------------------------------------------------+--------------------------------------+
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Load
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+---------------------------+-------------------------------------------------+--------------------------------------+
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| Instructions | Fusion condition | Fused instruction |
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+===========================+=================================================+======================================+
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| auipc rd_a, imm_a | rd_a == rd_b && rd_a == rs1_b | ld.pc rd_b, (imm_a + imm_b)pc |
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| ld rd_b, imm_b(rs1_b) | | |
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+---------------------------+-------------------------------------------------+--------------------------------------+
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| lui rd_a, imm_a | rd_a == rd_b && rd_a == rs1_b | ld rd_b, (imm_a + imm_b)x0 |
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| ld rd_b, imm_b(rs1_b) | | |
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+---------------------------+-------------------------------------------------+--------------------------------------+
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| add rd_a, rs1_a, rs2_a | rd_a == rd_b && rd_a == rs1_b && imm_b == 0 | ld.add rd_b, (rs1_a)(rs2_a) |
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| ld rd_b, imm_b(rs1_b) | | |
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+---------------------------+-------------------------------------------------+--------------------------------------+
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| sh1add rd_a, rs1_a, rs2_a | rd_a == rd_b && rd_a == rs1_b && imm_b == 0 | ld.sh1add rd_b, rs1_a, rs2_a |
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| ld rd_b, imm_b(rs1_b) | | |
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+---------------------------+-------------------------------------------------+--------------------------------------+
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---
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Fused instruction length
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+------+-------+-------+------+------+------+
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| fuse | RVC_2 | RVC_1 | len2 | len4 | len8 |
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+======+=======+=======+======+======+======+
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| 0 | 0 | 0 | 0 | 1 | 0 |
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| 0 | 0 | 1 | 1 | 0 | 0 |
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| 0 | 1 | 0 | 0 | 1 | 0 |
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| 0 | 1 | 1 | 1 | 0 | 0 |
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| 1 | 0 | 0 | 0 | 0 | 1 |
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| 1 | 0 | 1 | 1 | 1 | 0 |
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| 1 | 1 | 0 | 1 | 1 | 0 |
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| 1 | 1 | 1 | 0 | 1 | 0 |
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+------+-------+-------+------+------+------+

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