Support Zbs.

Author: Arnavion

README.md

@@ -26,6 +26,8 @@ The assembler only supports what the emulator implements. Per the [unprivileged
 
 - Zba 1.0.0 (address generation instructions)
 
+- Zbs 1.0.0 (single-bit instructions)
+
 Further extensions are not supported, notably instructions for hardware multiplication and division (M) and hardware floats (F, D).
 
 Compressed instructions are supported in the sense that the assembler will encode regular instructions like `add` and `lbu` into the compressed form when compression is enabled. The mnemonics for the compressed instructions like `c.add` and `c.lbu` are not supported. Instructions that only exist in compressed instruction extensions like `c.lwsp` can be written as `lwsp` or `c.lwsp`.
@@ -54,7 +56,7 @@ The assembler does not consider whether the target architecture is 32-bit or 64-
 
 Therefore the assembler also has a `--64` flag to explicitly set the target architecture to RV64I. When combined with the `--compress` flag it will instruct the assembler to not compress `jal`.
 
-The `*.c` files contain equivalent C solutions that can be put in [Compiler Explorer](https://gcc.godbolt.org/) with compiler set to `RISC-V (32-bits) gcc` or `RISC-V rv32gc clang` or corresponding 64-bit version, and flags set to `--std=c23 -Os -march=rv32id_zba_zicond` or `--std=c23 -Os -march=rv64id_zba_zicond`. Note that the assembler programs are hand-written and will not exactly match the compiler's output.
+The `*.c` files contain equivalent C solutions that can be put in [Compiler Explorer](https://gcc.godbolt.org/) with compiler set to `RISC-V (32-bits) gcc` or `RISC-V rv32gc clang` or corresponding 64-bit version, and flags set to `--std=c23 -Os -march=rv32id_zba_zbs_zicond` or `--std=c23 -Os -march=rv64id_zba_zbs_zicond`. Note that the assembler programs are hand-written and will not exactly match the compiler's output.
 
 The emulator has the Level Input and Level Output wired up to memory address `2^32 - 1`, which is why the assembler programs refer to `-1(zero)` and the C programs refer to `IO = (volatile uint8_t*)(intptr_t)-1;`.
 

freestanding/riscv64-arnavion-none-elf.json

@@ -7,7 +7,7 @@
 	"data-layout": "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128",
 	"eh-frame-header": false,
 	"emit-debug-gdb-scripts": false,
-	"features": "+forced-atomics,+zba,+zca,+zcb,+zicond,+zicsr,+zicntr",
+	"features": "+forced-atomics,+zba,+zbs,+zca,+zcb,+zicond,+zicsr,+zicntr",
 	"linker": "rust-lld",
 	"linker-flavor": "gnu-lld",
 	"llvm-target": "riscv64",

src/instruction.rs

@@ -853,15 +853,33 @@ instructions! {
 		#[u("auipc", Auipc)]
 		Auipc { dest: Register, imm: i32 },
 
+		#[r("bclr", Op)]
+		BClr { dest: Register, src1: Register, src2: Register },
+
+		#[i("bclri", OpImm)]
+		BClri { dest: Register, src: Register, shamt: i32 },
+
 		#[b("beq", Branch)]
 		Beq { src1: Register, src2: Register, offset: i32 },
 
+		#[r("bext", Op)]
+		BExt { dest: Register, src1: Register, src2: Register },
+
+		#[i("bexti", OpImm)]
+		BExti { dest: Register, src: Register, shamt: i32 },
+
 		#[b("bge", Branch)]
 		Bge { src1: Register, src2: Register, offset: i32 },
 
 		#[b("bgeu", Branch)]
 		Bgeu { src1: Register, src2: Register, offset: i32 },
 
+		#[r("binv", Op)]
+		BInv { dest: Register, src1: Register, src2: Register },
+
+		#[i("binvi", OpImm)]
+		BInvi { dest: Register, src: Register, shamt: i32 },
+
 		#[b("blt", Branch)]
 		Blt { src1: Register, src2: Register, offset: i32 },
 
@@ -871,6 +889,12 @@ instructions! {
 		#[b("bne", Branch)]
 		Bne { src1: Register, src2: Register, offset: i32 },
 
+		#[r("bset", Op)]
+		BSet { dest: Register, src1: Register, src2: Register },
+
+		#[i("bseti", OpImm)]
+		BSeti { dest: Register, src: Register, shamt: i32 },
+
 		#[r("czero.eqz", Op)]
 		CZeroEqz { dest: Register, src1: Register, src2: Register },
 
@@ -2237,12 +2261,20 @@ funct! {
 		Addw = 0b000,
 		And = 0b111,
 		Andi = 0b111,
+		BClr = 0b001,
+		BClri = 0b001,
+		BExt = 0b101,
+		BExti = 0b101,
 		Beq = 0b000,
 		Bge = 0b101,
 		Bgeu = 0b111,
+		BInv = 0b001,
+		BInvi = 0b001,
 		Blt = 0b100,
 		Bltu = 0b110,
 		Bne = 0b001,
+		BSet = 0b001,
+		BSeti = 0b001,
 		Csrrc = 0b011,
 		Csrrci = 0b111,
 		Csrrs = 0b010,
@@ -2303,6 +2335,14 @@ funct! {
 		Adduw = 0b000_0100,
 		Addw = 0b000_0000,
 		And = 0b000_0000,
+		BClr = 0b010_0100,
+		BClri = 0b010_0100,
+		BExt = 0b010_0100,
+		BExti = 0b010_0100,
+		BInv = 0b011_0100,
+		BInvi = 0b011_0100,
+		BSet = 0b001_0100,
+		BSeti = 0b001_0100,
 		CZeroEqz = 0b000_0111,
 		CZeroNez = 0b000_0111,
 		Or = 0b000_0000,

src/lib.rs

@@ -156,12 +156,22 @@ mod tests {
 			("auipc a0, -11", &[(0x5517, Some(0xffff))]),
 			("auipc a0, 11", &[(0xb517, Some(0x0000))]),
 
+			("bclr a0, a1, a2", &[(0x9533, Some(0x48c5))]),
+
+			("bclri a0, a1, 11", &[(0x9513, Some(0x48b5))]),
+			("bclri a0, a1, 31", &[(0x9513, Some(0x49f5))]),
+
 			("beq a0, a1, -4", &[(0x0ee3, Some(0xfeb5))]),
 			("beq a0, a1, 44", &[(0x0663, Some(0x02b5))]),
 
 			("beqz a0, -4", &[(0x0ee3, Some(0xfe05))]),
 			("beqz a0, 28", &[(0x0e63, Some(0x0005))]),
 
+			("bext a0, a1, a2", &[(0xd533, Some(0x48c5))]),
+
+			("bexti a0, a1, 11", &[(0xd513, Some(0x48b5))]),
+			("bexti a0, a1, 31", &[(0xd513, Some(0x49f5))]),
+
 			("bge a0, a1, -12", &[(0x5ae3, Some(0xfeb5))]),
 			("bge a0, a1, 36", &[(0x5263, Some(0x02b5))]),
 
@@ -180,6 +190,11 @@ mod tests {
 			("bgtz a0, -4", &[(0x4ee3, Some(0xfea0))]),
 			("bgtz a0, 12", &[(0x4663, Some(0x00a0))]),
 
+			("binv a0, a1, a2", &[(0x9533, Some(0x68c5))]),
+
+			("binvi a0, a1, 11", &[(0x9513, Some(0x68b5))]),
+			("binvi a0, a1, 31", &[(0x9513, Some(0x69f5))]),
+
 			("ble a0, a1, -20", &[(0xd6e3, Some(0xfea5))]),
 			("ble a0, a1, 12", &[(0xd663, Some(0x00a5))]),
 
@@ -204,6 +219,11 @@ mod tests {
 			("bnez a0, -28", &[(0x12e3, Some(0xfe05))]),
 			("bnez a0, 4", &[(0x1263, Some(0x0005))]),
 
+			("bset a0, a1, a2", &[(0x9533, Some(0x28c5))]),
+
+			("bseti a0, a1, 11", &[(0x9513, Some(0x28b5))]),
+			("bseti a0, a1, 31", &[(0x9513, Some(0x29f5))]),
+
 			("call -4", &[(0x0097, Some(0x0000)), (0x80e7, Some(0xffc0))]),
 			("call 24", &[(0x0097, Some(0x0000)), (0x80e7, Some(0x0180))]),
 			("call a0, -20", &[(0x0517, Some(0x0000)), (0x0567, Some(0xfec5))]),
@@ -605,6 +625,14 @@ mod tests {
 
 			("addw a0, a1, a2", &[(0x853b, Some(0x00c5))]),
 
+			("bclri a0, a1, 63", &[(0x9513, Some(0x4bf5))]),
+
+			("bexti a0, a1, 63", &[(0xd513, Some(0x4bf5))]),
+
+			("binvi a0, a1, 63", &[(0x9513, Some(0x6bf5))]),
+
+			("bseti a0, a1, 63", &[(0x9513, Some(0x2bf5))]),
+
 			("ld a0, -36", &[(0x0517, Some(0x0000)), (0x3503, Some(0xfdc5))]),
 			("ld a0, 72", &[(0x0517, Some(0x0000)), (0x3503, Some(0x0485))]),
 			("ld a0, -11(a1)", &[(0xb503, Some(0xff55))]),
@@ -766,10 +794,34 @@ mod tests {
 				sh1add a0, a1, a2
 				sh2add a0, a1, a2
 				sh3add a0, a1, a2
+				bclri a0, a1, 0
+				bclri a0, a1, 31
+				bseti a0, a1, 0
+				bseti a0, a1, 31
+				binvi a0, a1, 0
+				binvi a0, a1, 31
+				bexti a0, a1, 0
+				bexti a0, a1, 31
+				bclr a0, a1, a2
+				bset a0, a1, a2
+				binv a0, a1, a2
+				bext a0, a1, a2
 			", &[
 				(0xa533, 0x20c5),
 				(0xc533, 0x20c5),
 				(0xe533, 0x20c5),
+				(0x9513, 0x4805),
+				(0x9513, 0x49f5),
+				(0x9513, 0x2805),
+				(0x9513, 0x29f5),
+				(0x9513, 0x6805),
+				(0x9513, 0x69f5),
+				(0xd513, 0x4805),
+				(0xd513, 0x49f5),
+				(0x9533, 0x48c5),
+				(0x9533, 0x28c5),
+				(0x9533, 0x68c5),
+				(0xd533, 0x48c5),
 			]),
 
 			// bge.s
@@ -1405,13 +1457,21 @@ mod tests {
 				add.uw a0, a1, a2
 				zext.w a0, a1
 				slli.uw a0, a1, 2
+				bclri a0, a1, 63
+				bseti a0, a1, 63
+				binvi a0, a1, 63
+				bexti a0, a1, 63
 			", &[
 				(0xa53b, 0x20c5),
 				(0xc53b, 0x20c5),
 				(0xe53b, 0x20c5),
 				(0x853b, 0x08c5),
 				(0x853b, 0x0805),
 				(0x951b, 0x0825),
+				(0x9513, 0x4bf5),
+				(0x9513, 0x2bf5),
+				(0x9513, 0x6bf5),
+				(0xd513, 0x4bf5),
 			]),
 
 			// csr.s