156156/* Global Configuration Register */
157157#define DWC3_GCTL_PWRDNSCALE (n ) ((n) << 19)
158158#define DWC3_GCTL_U2RSTECN (1 << 16)
159- #define DWC3_GCTL_RAMCLKSEL (x ) (((x)& DWC3_GCTL_CLK_MASK) << 6)
159+ #define DWC3_GCTL_RAMCLKSEL (x ) (((x) & DWC3_GCTL_CLK_MASK) << 6)
160160#define DWC3_GCTL_CLK_BUS (0)
161161#define DWC3_GCTL_CLK_PIPE (1)
162162#define DWC3_GCTL_CLK_PIPEHALF (2)
184184#define DWC3_GUSB3PIPECTL_SUSPHY (1 << 17)
185185
186186/* Global TX Fifo Size Register */
187- #define DWC3_GTXFIFOSIZ_TXFDEF (n ) ((n)& 0xffff)
188- #define DWC3_GTXFIFOSIZ_TXFSTADDR (n ) ((n)& 0xffff0000)
187+ #define DWC3_GTXFIFOSIZ_TXFDEF (n ) ((n) & 0xffff)
188+ #define DWC3_GTXFIFOSIZ_TXFSTADDR (n ) ((n) & 0xffff0000)
189189
190190/* Global HWPARAMS1 Register */
191191#define DWC3_GHWPARAMS1_EN_PWROPT (n ) (((n) & (3 << 24)) >> 24)
283283#define DWC3_DSTS_DEVCTRLHLT (1 << 22)
284284
285285#define DWC3_DSTS_USBLNKST_MASK (0x0f << 18)
286- #define DWC3_DSTS_USBLNKST (n ) (((n)& DWC3_DSTS_USBLNKST_MASK) >> 18)
286+ #define DWC3_DSTS_USBLNKST (n ) (((n) & DWC3_DSTS_USBLNKST_MASK) >> 18)
287287
288288#define DWC3_DSTS_RXFIFOEMPTY (1 << 17)
289289
290290#define DWC3_DSTS_SOFFN_MASK (0x3fff << 3)
291- #define DWC3_DSTS_SOFFN (n ) (((n)& DWC3_DSTS_SOFFN_MASK) >> 3)
291+ #define DWC3_DSTS_SOFFN (n ) (((n) & DWC3_DSTS_SOFFN_MASK) >> 3)
292292
293293#define DWC3_DSTS_CONNECTSPD (7 << 0)
294294
@@ -396,8 +396,8 @@ enum dwc3_link_state {
396396
397397/* TRB Length, PCM and Status */
398398#define DWC3_TRB_SIZE_MASK (0x00ffffff)
399- #define DWC3_TRB_SIZE_LENGTH (n ) ((n)& DWC3_TRB_SIZE_MASK)
400- #define DWC3_TRB_SIZE_PCM1 (n ) (((n)& 0x03) << 24)
399+ #define DWC3_TRB_SIZE_LENGTH (n ) ((n) & DWC3_TRB_SIZE_MASK)
400+ #define DWC3_TRB_SIZE_PCM1 (n ) (((n) & 0x03) << 24)
401401#define DWC3_TRB_SIZE_TRBSTS (n ) (((n) & (0x0f << 28)) >> 28)
402402
403403#define DWC3_TRBSTS_OK 0
@@ -410,10 +410,10 @@ enum dwc3_link_state {
410410#define DWC3_TRB_CTRL_LST (1 << 1)
411411#define DWC3_TRB_CTRL_CHN (1 << 2)
412412#define DWC3_TRB_CTRL_CSP (1 << 3)
413- #define DWC3_TRB_CTRL_TRBCTL (n ) (((n)& 0x3f) << 4)
413+ #define DWC3_TRB_CTRL_TRBCTL (n ) (((n) & 0x3f) << 4)
414414#define DWC3_TRB_CTRL_ISP_IMI (1 << 10)
415415#define DWC3_TRB_CTRL_IOC (1 << 11)
416- #define DWC3_TRB_CTRL_SID_SOFN (n ) (((n)& 0xffff) << 14)
416+ #define DWC3_TRB_CTRL_SID_SOFN (n ) (((n) & 0xffff) << 14)
417417
418418#define DWC3_TRBCTL_NORMAL DWC3_TRB_CTRL_TRBCTL(1)
419419#define DWC3_TRBCTL_CONTROL_SETUP DWC3_TRB_CTRL_TRBCTL(2)
@@ -439,14 +439,14 @@ struct dwc3_trb {
439439} PACKED ;
440440
441441/* HWPARAMS0 */
442- #define DWC3_MODE (n ) ((n)& 0x7)
442+ #define DWC3_MODE (n ) ((n) & 0x7)
443443
444444#define DWC3_MODE_DEVICE 0
445445#define DWC3_MODE_HOST 1
446446#define DWC3_MODE_DRD 2
447447#define DWC3_MODE_HUB 3
448448
449- #define DWC3_MDWIDTH (n ) (((n)& 0xff00) >> 8)
449+ #define DWC3_MDWIDTH (n ) (((n) & 0xff00) >> 8)
450450
451451/* HWPARAMS1 */
452452#define DWC3_NUM_INT (n ) (((n) & (0x3f << 15)) >> 15)
@@ -458,7 +458,7 @@ struct dwc3_trb {
458458#define DWC3_NUM_IN_EPS (p ) (((p)->hwparams3 & (DWC3_NUM_IN_EPS_MASK)) >> 18)
459459
460460/* HWPARAMS7 */
461- #define DWC3_RAM1_DEPTH (n ) ((n)& 0xffff)
461+ #define DWC3_RAM1_DEPTH (n ) ((n) & 0xffff)
462462
463463#define DWC3_REVISION_173A 0x5533173a
464464#define DWC3_REVISION_175A 0x5533175a
@@ -605,20 +605,20 @@ union dwc3_event {
605605 struct dwc3_event_gevt gevt ;
606606};
607607
608- #define DWC3_DEPCFG_EP_TYPE (n ) (((n)& 0x3) << 1)
609- #define DWC3_DEPCFG_EP_NUMBER (n ) (((n)& 0x1f) << 25)
610- #define DWC3_DEPCFG_FIFO_NUMBER (n ) (((n)& 0xf) << 17)
611- #define DWC3_DEPCFG_MAX_PACKET_SIZE (n ) (((n)& 0x7ff) << 3)
608+ #define DWC3_DEPCFG_EP_TYPE (n ) (((n) & 0x3) << 1)
609+ #define DWC3_DEPCFG_EP_NUMBER (n ) (((n) & 0x1f) << 25)
610+ #define DWC3_DEPCFG_FIFO_NUMBER (n ) (((n) & 0xf) << 17)
611+ #define DWC3_DEPCFG_MAX_PACKET_SIZE (n ) (((n) & 0x7ff) << 3)
612612
613- #define DWC3_DEPCFG_INT_NUM (n ) (((n)& 0x1f) << 0)
613+ #define DWC3_DEPCFG_INT_NUM (n ) (((n) & 0x1f) << 0)
614614#define DWC3_DEPCFG_XFER_COMPLETE_EN BIT(8)
615615#define DWC3_DEPCFG_XFER_IN_PROGRESS_EN BIT(9)
616616#define DWC3_DEPCFG_XFER_NOT_READY_EN BIT(10)
617617#define DWC3_DEPCFG_FIFO_ERROR_EN BIT(11)
618618#define DWC3_DEPCFG_STREAM_EVENT_EN BIT(13)
619- #define DWC3_DEPCFG_BINTERVAL_M1 (n ) (((n)& 0xff) << 16)
619+ #define DWC3_DEPCFG_BINTERVAL_M1 (n ) (((n) & 0xff) << 16)
620620#define DWC3_DEPCFG_STREAM_CAPABLE BIT(24)
621- #define DWC3_DEPCFG_EP_NUMBER (n ) (((n)& 0x1f) << 25)
621+ #define DWC3_DEPCFG_EP_NUMBER (n ) (((n) & 0x1f) << 25)
622622#define DWC3_DEPCFG_BULK_BASED BIT(30)
623623#define DWC3_DEPCFG_FIFO_BASED BIT(31)
624624
0 commit comments