✨ feat(compiler): Support operand-less instructions and fix parser crash

Author: TaiHusk

README.md

@@ -1,5 +1,7 @@
 # AsmX G3 Compiler
 
+[ChangeLog](./changelog)
+
 ## Command Line Interface (CLI) Usage
 
 ### Installation

changelog

@@ -0,0 +1,61 @@
+### **Changelog: rev 2.0**
+
+This release introduces a critical stability fix for the compiler and expands the supported `amd64` instruction set. The revision is updated from `1.0` to `2.0` to reflect these significant improvements.
+
+---
+
+### **Bug Fixes**
+
+*   **Compiler: Resolved a critical null reference error during instruction parsing.**
+
+    A recurring internal system error that caused an `Unhandled Rejection` has been fixed. This error occurred when the compiler's parser attempted to process instructions that have no operands.
+
+    **Symptom:** The compiler would crash with the following error message, preventing the assembly of valid code that included operand-less instructions.
+    ```
+    ✘ Unhandled Rejection, Reason: Cannot read properties of undefined (reading 'type')
+    ```
+
+    **Root Cause:** The `zcc_build_generic_instruction` method directly accessed `ast[0].type` without first verifying that the `ast[0]` element existed. For instructions without operands, this `ast[0]` was `undefined`, leading to a `TypeError` and a compiler crash.
+
+    **Solution:** The code has been patched to use optional chaining (`?.`). The condition is now `ast[0]?.type`, which safely checks for the existence of `ast[0]` and its `type` property before attempting to access it. This ensures that operand-less instructions are handled gracefully by the parser.
+
+    **Before:**
+    ```javascript
+      static zcc_build_generic_instruction(ast) {
+        if (ast[0].type == TypeOfAtomicExpression.ARGUMENTS) { // Crashes if ast[0] is undefined
+          return ast[0].body.values;
+        }
+        return ast;
+      }
+    ```
+
+    **After (Fix Implemented):**
+    ```javascript
+      static zcc_build_generic_instruction(ast) {
+        if (ast[0]?.type && ast[0].type == TypeOfAtomicExpression.ARGUMENTS) { // Safely checks for existence
+          return ast[0].body.values;
+        }
+        return ast;
+      }
+    ```
+
+### **New Features**
+
+*   **Instruction Set: Added support for common `amd64` instructions without operands.**
+
+    To enhance low-level programming capabilities, the instruction set has been updated to include several fundamental `amd64` instructions that do not take any operands.
+
+    The following instructions are now fully supported:
+    *   `nop`: No Operation
+    *   `fwait`: Check pending unmasked floating-point exceptions
+    *   `pushf`: Push rFLAGS Register onto the Stack
+    *   `popf`: Pop Stack into rFLAGS Register
+    *   `sahf`: Store AH into Flags
+    *   `lahf`: Load Status Flags into AH Register
+
+    **Implementation:** These instructions have been mapped within the compiler's `instructionSet`, allowing the assembler to correctly recognize and encode them.
+
+### **Developer Impact**
+
+Developers can now write code utilizing these common, operand-less instructions without encountering a compiler crash. This fix removes a significant blocker and enables more flexible and direct low-level code generation.
+

src/ast/builder.instruction.js

@@ -149,7 +149,7 @@ class BuilderExpression {
   }
 
   static zcc_build_generic_instruction(ast) {
-    if (ast[0].type == TypeOfAtomicExpression.ARGUMENTS) {
+    if (ast[0]?.type && ast[0].type == TypeOfAtomicExpression.ARGUMENTS) {
       return ast[0].body.values;
     }
     return ast;

src/backend/targets/x86_64/hwm/tbl.cjs

@@ -361,6 +361,65 @@ class AssemblyInstructionDescriptorTable {
             };
             this.instructionSet.set('lea', leaDef);
         });
+        const instructions_without_operands_map = [
+            {
+                mnemonic: 'nop',
+                variants: [
+                    {
+                        opcode: [0x90],
+                        operands: []
+                    }
+                ]
+            },
+            {
+                mnemonic: 'fwait',
+                variants: [
+                    {
+                        opcode: [0x9B],
+                        operands: []
+                    }
+                ]
+            },
+            {
+                mnemonic: 'pushf',
+                variants: [
+                    {
+                        opcode: [0x9C],
+                        operands: []
+                    }
+                ]
+            },
+            {
+                mnemonic: 'popf',
+                variants: [
+                    {
+                        opcode: [0x9D],
+                        operands: []
+                    }
+                ]
+            },
+            {
+                mnemonic: 'sahf',
+                variants: [
+                    {
+                        opcode: [0x9E],
+                        operands: []
+                    }
+                ]
+            },
+            {
+                mnemonic: 'lahf',
+                variants: [
+                    {
+                        opcode: [0x9F],
+                        operands: []
+                    }
+                ]
+            }
+        ];
+        for (const instruction_define of instructions_without_operands_map) {
+            this.instructionSet.set(instruction_define.mnemonic, instruction_define);
+        }
     }
     static getInstructionSet() {
         return this.instructionSet;

src/backend/targets/x86_64/hwm/tbl.cts

@@ -378,6 +378,67 @@ export class AssemblyInstructionDescriptorTable {
       };
       this.instructionSet.set('lea', leaDef);
     });
+
+    const instructions_without_operands_map: InstructionDefinition[] = [
+      {
+        mnemonic: 'nop',
+        variants: [
+          {
+            opcode: [0x90],
+            operands: []
+          }
+        ]
+      },
+      {
+        mnemonic: 'fwait',
+        variants: [
+          {
+            opcode: [0x9B],
+            operands: []
+          }
+        ]
+      },
+      {
+        mnemonic: 'pushf',
+        variants: [
+          {
+            opcode: [0x9C],
+            operands: []
+          }
+        ]
+      },
+      {
+        mnemonic: 'popf',
+        variants: [
+          {
+            opcode: [0x9D],
+            operands: []
+          }
+        ]
+      },
+      {
+        mnemonic: 'sahf',
+        variants: [
+          {
+            opcode: [0x9E],
+            operands: []
+          }
+        ]
+      },
+      {
+        mnemonic: 'lahf',
+        variants: [
+          {
+            opcode: [0x9F],
+            operands: []
+          }
+        ]
+      }
+    ];
+
+    for (const instruction_define of instructions_without_operands_map) {
+      this.instructionSet.set(instruction_define.mnemonic as string, instruction_define);
+    }
   }
 
   public static getInstructionSet(): Map<string, InstructionDefinition> {

src/kernel.js

@@ -70,7 +70,7 @@ function helper() {
   journal_composer_TL3('Compilation Options:');
   journal_composer_TL3("  -r, --release           Create a executable file");
   journal_composer_TL3("  -o, --objname           Set the output file name");
-  journal_composer_TL3("  -m, --march             Specify the target CPU architecture (x86_64, riscv, or arm64) for compilation");
+  journal_composer_TL3("  -m, --march             Specify the target CPU architecture (x86_64, x64, amd64) for compilation");
   journal_composer_TL3('Commands:');
   journal_composer_TL3('  --update                Update AsmX compilation platform');
 }
@@ -81,7 +81,7 @@ function version() {
 }
 
 function dumpversion() {
-  Server.journal.log('Version: v28 (rev 1.0)');
+  Server.journal.log('Version: v28 (rev 2.0)');
 }
 
 function dumpmachine() {